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System-On-a-Chip Design

ELECT 1002. System-On-a-Chip Design. SoC Challenges & Transaction Level Modeling (TLM). Dr. Eng. Amr T. Abdel-Hamid. Spring 2008. Table Of Contents. SoC Challenges TLM Model Concepts TLMs for different design domains. SoC Challenges. Explosive Complexity: The smaller the better

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System-On-a-Chip Design

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  1. ELECT 1002 System-On-a-Chip Design SoC Challenges & Transaction Level Modeling (TLM) Dr. Eng. Amr T. Abdel-Hamid Spring 2008

  2. Table Of Contents • SoC Challenges • TLM Model Concepts • TLMs for different design domains

  3. SoC Challenges • Explosive Complexity: • The smaller the better • Time-to-market • the amount of time required for conceiving an idea into a real product for sales Shorter times-to-market • Sky-rocketing Cost

  4. System Design Level

  5. Solutions • TLM • Reuse of implementations (IP Design Reuse) • System standards

  6. Classic Design Flow Algorithmic Design Architectural Design System Level Design (Co-design Level) Behavioral Model (Spec.) Partitioning RTL Implementation VHDL/Verilog RTL Model S/W Design Software Implementation H/W Design Gate Synthesis Gate Model Synthesis Tools Layout Generation Layout System Integration

  7. System Description Models • Transistor level • HSpice, Schematic • Gate level • Netlist, PALASM, TEGAS • RT Level • HDLs

  8. Modern Design Flow

  9. Levels of Abstraction Three levels of abstraction: • Functional level • Executable Specification • Un-Timed • Architecture level • Analyze SoC architecture • Early SW development • Estimated timing • Micro-Architecture level • Pin level • RTL/Behavioral HW design • Exact Timing

  10. Transaction Level Modeling - TLM • Transaction is the exchange of data or an event between two component of a modeled and simulated system • data can be anything from a word to a complex data structure • event transaction models synchronization aspects that ensure correct operation of the SoC • The behavior of functional blocks can be separated from communication • The communication is described in terms of sending transactions TLM only focus on mapping out data flow details, i.e. the type of data that flows and where it is stored

  11. TLM – cont. • RTL: • The bus is wires • Each device on the bus has a pin-accurate interface • Each device interface must implement the bus protocol • TLM: • Bus model enforces the bus protocol • Each device communicates via transaction level API • Less code, fewer pins, fewer • events => much faster

  12. Basics of TLM Transaction : exchange of a data or an event between two components of a modeled and simulated system Module : structural entity, which contain processes, ports, channels, and other modules Channel : implements one or more interfaces, and serves as a container for communication functionality Port : object through which a module can access a channel’s interface.

  13. Basics of TLM Primitive & Hierarchical Channel • Hierarchical channels contain processes, ports, modules and channels, but primitive channels do not

  14. TLM Advantages • SW development delay SW team can begin SW developing or testing stage much sooner • HW/SW communication HW parts can communicate with SW parts in this common environment. Makes the SW debug easier. • Design space exploration Designers can decide on its partitioning (module and HW/SW partitioning) in the early stages of the design. • Simulation speed The number of events decreases

  15. TLM Abstraction Models • Time granularity for communication/computation objects can be classified into 3 basic categories. • Models B, C, D and E could be classified as TLMs.

  16. TLM Abstraction Models • Specification model • PE*-assembly model or Component Assembly • Bus-arbitration model • Time-accurate communication model • Cycle-accurate computation model • Implementation model * Processing elements

  17. A: “Specification Model” • Objects • Computation • -Behaviors • Communication • -Variables • Composition • Hierarchy • Order • Sequential • Parallel • Piped • States • Synchronization • Notify/Wait

  18. B: “Component-Assembly Model” • Composition • Hierarchy • Order • Sequential • Parallel • Piped • States • Synchronization • Notify/Wait • Objects • Computation • - Proc • - IPs • - Memories • Communication • -Variable channels

  19. C: “Bus-Arbitration Model” • Objects • Computation • - Proc • - IPs (Arbiters) • - Memories • Communication • - Abstract bus channels • Composition • Hierarchy • Order • Sequential • Parallel • Piped • States • Synchronization • Notify/Wait Bus arbiter arbitrates bus conflict

  20. D: “Bus-Functional Model” • Objects • Computation • - Proc • - IPs (Arbiters) • - Memories • Communication • - Protocol bus channels • Composition • Hierarchy • Order • Sequential • Parallel • Piped • States • Synchronization • Notify/Wait • Time/cycle accurate communication (time constraint) • Approximate timed computation • Protocol channel provides functions for all abstraction bus transaction

  21. E: “Cycle-Accurate Computation Model” • Composition • Hierarchy • Order • Sequential • Parallel • Piped • States • Synchronization • Notify/Wait • Objects • Computation • - Proc • - IPs (Arbiters) • - Memories • - Wrappers • Communication • - Abstract bus channels • Modeled at register-transfer level • PE are pin accurate and execute cycle-accurately • Wrappers convert data transfer from higher level of abstraction to lower level abstraction

  22. F: “Implementation Model” • Objects • Computation • - Proc • - IPs (Arbiters) • - Memories • Communication • -Buses (wires) • Composition • Hierarchy • Order • Sequential • Parallel • Piped • States • Synchronization • Notify/Wait

  23. SOC Design Tasks Specificationmodel 1 PE-assembly model 2 7 8 3 5 Time-accurate Communication model Cycle-accurate Computation model 4 Implementation model 6 1. PE assembly and model generation 2. Communication exploration and bus-arbitration model generation 3. Protocol refinement and time-accurate communication model generation System Design 4. RTL/ISS* synthesis Bus-arbitrationmodel 5. IP replacement 6. Interconnect network generation 7. Accurate communication feedback 8. Accurate computation feedback Component Design * ISS : Instruction set simulator

  24. SOC Design Tasks 4 3 6 5 2 1

  25. Characteristics of Different Abstraction Models

  26. References The credit of these slides goes to: D. Gajski, L. Cai, “Transaction Level Modeling: An Overview”, Center for Embedded Computer Systems, University of California, Irvine, 2004. Z. Navabi, “The Role of SystemC in theEvolution of Hardware Design”, Worcester Polytechnic Institute. B. Vanthournout, “SoC design methodology Using SystemC”, Coware, 2003. F. Ghenassia, “Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems, Springer, 2005. & Others

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