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Fabrication Process

Lithography Resist coating + soft bake Exposure Post-exposure bake + development Etching Silicon etch Oxide Etch Post processing Dicing Substrate thinning Cleaving. Fabrication Process. Layer structure 205 Top Si layer 400nm Buried Oxide Wafer size 8” (200mm).

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Fabrication Process

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  1. Lithography Resist coating + soft bake Exposure Post-exposure bake + development Etching Silicon etch Oxide Etch Post processing Dicing Substrate thinning Cleaving Fabrication Process

  2. Layer structure 205 Top Si layer 400nm Buried Oxide Wafer size 8” (200mm) Step 1: Bare SOI wafer 205nm Si SiO2 400nm Si-substrate

  3. Resist Shipley UV3 800nm thick Photoresist Step 2: Photoresist Coating

  4. Step 3: Soft baking of resist Photoresist

  5. AR coating No standing waves in resistduring lithography 40nm of NFC Step 4: Antireflective coating AR-coating

  6. Step 5: Illumination • Deep UV Lithography • Wavelength = 248nm • NA = 0.63 • Dose = 10-40 mJ • Reduction = 4X

  7. Step 6: Post-exposure bake

  8. Step 7: Development

  9. Etch properties TCP9400PTX ICP-RIE Low pressure /high density Cl2/HBr/He/O2 chemistry Two-step break-through main etch Step 8: Silicon etch

  10. Etch properties Exelan Dual frequency Medium pressure /medium density CF4/CHF3 chemistry Step 9: Oxide Etch

  11. Step 10: Resist strip

  12. Substrate thinning = dangerous Step 11: Protective Resist Layer • 1-3m resist cover 750m Wafer is diced into 3 x 3 cm2 dies for substrate thinning

  13. Glue = Bee’s wax Heated to ± 130°C Bee’s wax Glass plate Step 12: Glue on glass plate

  14. Mechanical grinding Alumina powder 5-8 hours Remove 500m 250m Bee’s wax Glass plate Step 13: Substrate thinning

  15. Step 14: Cleaning and Cleaving

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