Interconnect Driver Design for Long Wires in FPGAs

1. Interconnect Driver Design for Long Wires in FPGAs Edmund Lee, Guy Lemieux & Shahriar Mirabbasi University of British Columbia, Canada Electrical & Computer Engineering FPT 2006 Presentation

2. What this talk is about… • Investigate the circuit design of switch drivers for long wires in FPGAs • Topics considered • Driver circuit design • Wirelengths in FPGA architecture • Midpoint delays

3. Outline • Motivation • Problem Description • Background • Driver Design Approaches • Method 1: Elmore-based • Method 2: SPICE-based • CAD Modeling, VPR Results • Summary

4. Unidirectional interconnect Motivation • Deep submicron interconnect delay is increasing • Interconnect delay is a large component of FPGA delay • Evolution of FPGA Switch Drivers • Bidirectional  Unidirectional routing Bidirectional interconnect

5. Motivation … • Only part of a wire is used in FPGAs • critical sink locations are unknown • can we improve all midpoint delays? Sink1 Sink2 Sink3 Sink4

6. Problem Description Given: Wire RC, total wire length Find: Buffer sizes, buffer locations, # of buffers

7. Background

8. Method 1: Elmore-based Design • Provide circuit design solution • Elmore delay model • Multidimensional sweep • determine optimal wirelengths and buffersizes • Fix B1 to minimum size 3 stage distributed design

9. 100% 100% 45% 55% 50% 50% Elmore-based Design Results * Buffer 1 is fixed to minimum size

10. Elmore-based Design Results • Results • Distributed buffering is best with wires > 2mm • For all wirelengths, L1 = 0 • Delay is tolerant to shifts in buffer placement • Limitations • Complexity related to number of stages • RC based Elmore approach • Difficult to model multiplexer circuits • Accuracy (delay and determining sizes)

11. Method 2: Spice-Based Design Designs with best delay/mm Divide, characterize and combine… multiplexed (mux) distributed (distrib) Characterization: design(wirelength)  buffersizes and delays

12. Buffer-Wire Pre-Characterization Distributed (distrib) Buffersize Wirelength

13. Delay Concatenation • Sum delays of each stage together • Fast to compute • Accurate (within 4% of HSPICE) Mux stage delay Distributed stage delay = + Delay x (N-1)

14. L0-Sweep • Remaining Unknowns: • L0 (mux stage length) • L1 (distributed stage length) • Length = L0 + L1*(N – 1) • Sweep L0 for a fixed N ? ? ? Length

15. 2 stage (N=2) Dist Mux L0 L1 L0-Sweep

16. Spice-Based Design Conclusions • Distributed designs improve over lumped designs on wires longer than 2mm+ • Longer wires achieve faster delay/mm • In an FPGA  Multiplexing Interval MultiplexingInterval

17. Multiplexing Interval

18. Lumped driver What about Early Turns? • Path Delay Profiles show potential improvement of the proposed circuit designs

19. VPR Modifications • Assess the benefits of distributed buffering design on FPGAs • Early Turn Model • Can compute a path delay profile for VPR • Fast Path modeling

20. Prior FPT04 Design Distributed Lumped driver Distributed + Fast Lumped + ETM VPR Results MCNC Benchmarks

21. Summary • Developed interconnect driver design methodology for FPGAs • Accounts for multiplexers • Examined early turns • Identified that longer wires can improve delay efficiency in FPGAs • Results from VPR • Early turn modeling (5-10%) • Distributed buffers (2-3%) • Fast path (4-9%)