COMP541 State Machines – 2 Registers and Counters

1. COMP541State Machines – 2Registers and Counters Montek Singh Feb 11, 2010

2. Topics • Lab preview • Verilog styles for FSM • Don’t forget to check synthesis output and console msgs. • State machine styles • Moore vs. Mealy • Building blocks: registers and counters

3. Lab Preview: Buttons and Debouncing • Button normally high • press pulls it low • Mechanical switches “bounce” • vibrations cause them to go to 1 and 0 a number of times • hundreds of times! • We’ll want to • “Debounce”: Any ideas? • Synchronize with clock • Think about: • What does it mean to “press the button”? Think carefully!! • What if button is held down for a long time?

4. Verilog Styles for FSM • Try to explain what synthesizer is doing • Read the messages on the console

5. Pitfall: Beware of Unexpected Latches! • You can easily specify latches unexpectedly • Hangover from programming in C…! • always will try to synthesize FF: if (select) out <= A; if (!select) out <= B; • FF added to save old value if condition is false • To avoid extra FF, cover all possibilities: if (select) out <= A; else out <= B;

6. FSM Verilog: Using One Always Block always@(posedgeclk) begin case (state) s1: if (x1 == 1'b1) begin state <= s2; outp <= 1'b1; end else begin state <= s3; outp <= 1'b0; end s2: begin state <= s4; outp <= 1'b1; end s3: begin state <= s4; outp <= 1'b0; end s4: begin state <= s1; outp <= 1'b0; end endcase end ~x1

7. Synthesis Output Synthesizing Unit <v_fsm_1>. Related source file is "v_fsm_1.v". Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 4 | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset State | 00 | | Power Up State | 00 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <outp>. Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s).

8. Split Output Off • Separate always for outp

9. Code always @(posedge clk) case (state) s1: if (x1 == 1'b1) state <= s2; else state <= s3; s2: state <= s4; s3: state <= s4; s4: state <= s1; endcase always @(state) case (state) s1: outp <= 1'b1; s2: outp <= 1'b1; s3: outp <= 1'b0; s4: outp <= 1'b0; endcase

10. Synthesis (no latch) Synthesizing Unit <v_fsm_2>. Related source file is "v_fsm_2.v". Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 1 | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset State | 00 | | Power Up State | 00 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit <v_fsm_2> synthesized.

11. Textbook Uses 3 always Blocks

12. Three always Blocks always @(posedgeclk) begin state <= next_state; end always @(state or x1) begin case (state) s1: if (x1==1'b1) next_state <= s2; else next_state <= s3; s2: next_state <= s4; s3: next_state <= s4; s4: next_state <= s1; endcase end always @(state) begin case (state) s1: outp <= 1'b1; s2: outp <= 1'b1; s3: outp <= 1'b0; s4: outp <= 1'b0; endcase end

13. Synthesis (again, no latch) Synthesizing Unit <v_fsm_3>. Related source file is "v_fsm_3.v". Found finite state machine <FSM_0> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 1 | | Clock | clk (rising_edge) | | Reset | reset (positive) | | Reset type | asynchronous | | Reset State | 00 | | Power Up State | 00 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit <v_fsm_3> synthesized.

14. My Preference • The one with 2 always blocks • Less prone to error than 1 always • Easy to visualize the state transitions

15. State Encoding • So far we’ve used binary encoding • Not necessarily best • XST chooses one to minimize hardware • Can change by right-clicking Synthesize-XST • Possible encodings next slides

16. Gray Code (synthesis output) ============================================================ * Advanced HDL Synthesis * ============================================================ Analyzing FSM <FSM_0> for best encoding. Optimizing FSM <state> on signal <state[1:2]> with gray encoding. ------------------- State | Encoding ------------------- 00 | 00 01 | 01 10 | 11 11 | 10 -------------------

17. One-Hot Encoding Optimizing FSM <state> on signal <state[1:4]> with one-hot encoding. ------------------- State | Encoding ------------------- 00 | 0001 01 | 0010 10 | 0100 11 | 1000 ------------------- Hmmm, state register grew. What’s up?

18. Safe Implementation Mode “XST can add logic to your FSM implementation that will let your state machine recover from an invalid state. If during its execution, a state machine gets into an invalid state, the logic added by XST will bring it back to a known state, called a recovery state. This is known as Safe Implementation mode.” from XST manual

19. Moore vs. Mealy FSMs? • So, is there a practical difference?

20. Moore vs Mealy Recognizer Mealy FSM: arcs indicate input/output

21. Moore and Mealy Timing Diagram

22. Moore vs. Mealy FSM Schematic • Moore • Mealy

23. Registers and Counters: Definitions • Register – a set of flip-flops • May include extensive logic to control state transition • May allow shifting • register also refers to fast memory for storing data in a computer • Counter • Register that goes through sequence of states as it is clocked

24. Simple Register • Store D • On posedge of Clock • Clear signal normally high • Power-up reset • Symbol

25. Clocking • Typically don’t want to load every clock • Can gate the clock • But added clock skew is a problem

26. Enable • If load H, then D is gated through • Otherwise, Q is fed back • Keep same value • No clock gating • Did this because D FF doesn’t have a “no change” behavior

27. Counters • Counter is a register – has state • Also goes through sequence of states – counts – on clock or other pulses • Binary counter • Counts through binary sequence • n bit counter counts from 0 to 2n

28. Ripple Counter • Simple • So Q will alternate 1 and 0 • Why called ripple counter?

29. Synchronous Counters • Ripple counter is easy • rippling nature may cause problems, though • delay increases with bit width! • Synchronous counter most common • meaning every flip-flop is driven by the same clock

30. Synchronous Counter • Same clock fed to all flip-flops • But… • delay again increases with bit width

31. Parallel Design • Now “constant” delay • higher order bits need gates with more fan-in though • Can gang these to make longer serial-parallel counter

32. Verilog Counter (simple) module count (CLK, EN, Q); input CLK, EN; output [3:0] Q; reg [3:0] Q; always@(posedge CLK) begin if (EN) Q <= Q + 4'b0001; end endmodule

33. Verilog Counter (from book) module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] Q; assign CO = (count == 4'b1111 && EN == 1’b1) ? 1 : 0; always@(posedge CLK or posedge RESET) begin if (RESET) Q <= 4'b0000; else if (EN) Q <= Q + 4'b0001; end endmodule

34. Arbitrary Count • One more type of counter is useful • Count an arbitrary sequence • maybe you need a sequence of states • maybe a pseudo-random sequence

35. Circuit and State Diagram

36. Shift Registers • Capability to shift bits • In one or both directions • Why? • Part of standard CPU instruction set • Cheap multiplication • Serial communications • Just a chain of flip-flops

37. Simple 4-Bit Shift Register • Clocked in common • Just serial in and serial out • Is this a FIFO?

38. Verilog for Simple 4-bit Shift Register module srg_4_r (CLK, SI, Q, SO); input CLK, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; always@(posedge CLK) begin Q <= {Q[2:0], SI}; end endmodule

39. Symbol • How about enabling/disabling? • We could gate the clock • But have to potentially deal with skew • Usually an enable provided

40. Parallel Load • Can provide parallel outputs from flip-flops • And also parallel inputs

41. Schematic Detail Next

42. Detail

43. Why is this useful? • Basis for serial communications • Keyboard • Serial port • Initially to connect to terminals • Now mainly for modem • USB • Firewire

44. Example Could shift data in, or parallel load What’s on wire at each clock? Clocked 4 times

45. Table Showing Shift

46. Serial vs. Parallel Transfer • Parallel transfer – over as many wires as word (for example) • Serial transfer – over a single wire • Trade time for wires • Takes n times longer • although lately, may have speed advantages over parallel in very high-speed scenarios • e.g., USB (Universal Serial Bus)

47. Bidirectional Shift Register • Shift either way • Now we have following possible inputs • Parallel load • Shift from left • Shift from right • Also “no change” • Schematic next

48. Schematic

49. Next Week • How to generate a VGA signal • Timing of sequential logic • Then on to • Arithmetic circuits • Memories