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Development of DC-DC converter ASICs

Development of DC-DC converter ASICs. S.Michelis 1,3 , B.Allongue 1 , G.Blanchot 1 , F.Faccio 1 , C.Fuentes 1,2 , S.Orlandi 1 , S.Saggini 4 1 CERN – PH-ESE 2 UTFSM, Valparaiso, Chile 3 EPFL, Lausanne 4 University of Udine. ATLAS–CMS Power Working Group 31/03/2010. Outline. AMIS2

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Development of DC-DC converter ASICs

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  1. Development of DC-DC converter ASICs S.Michelis1,3,B.Allongue1, G.Blanchot1, F.Faccio1, C.Fuentes1,2, S.Orlandi1, S.Saggini4 1CERN – PH-ESE 2UTFSM, Valparaiso, Chile 3EPFL, Lausanne 4University of Udine ATLAS–CMS Power Working Group 31/03/2010

  2. Outline • AMIS2 • New results with AMIS2 • Proton irradiation • Efficiency in QFN32 package • ASIC designed in IHP technology • Features • From IHP1 to IHP2 • Overcurrent protection • Bandgap • Schedule 2 S.Michelis CERN/PH

  3. Internal oscillator Internal voltage reference Programmable delay between gate signals Integrated feedback loop with bandwidth of 20Khz TID radiation tolerance up to 300Mrad Already used and tested in Aachen and Fermilab AMIS2 prototype Annealing 3 days Annealing 7 days Pre rad Details presented at TWEPP09 (http://indico.cern.ch/contributionDisplay.py?contribId=97&sessionId=42&confId=49682) S.Michelis CERN/PH

  4. AMIS2 proton irradiation Please note that the pre-rad results are taken with different bonding setup. These results are shown only to compare the efficiency trend • AMIS2 has been irradiated with proton at the CERN “irrad1” facility (24 GeV/c proton beam from PS). Two different different proton fluences have been reached: 2 1015 p/cm2 and 5 1015 p/cm2 Therefore we have a prototype in the backup technology that is fully functional with TID up to 300Mrd and proton fluence up to 5 1015 p/cm2 S.Michelis CERN/PH

  5. Package QFN48 Package QFN32 7 mm 5 mm 7 mm 5 mm AMIS2 package 5 S.Michelis CERN/PH

  6. AMIS2 QFN32 efficiency Efficiency with new board and new package has been extracted. Higher efficiency is measured in comparison with QFN48 in particular for higher load S.Michelis CERN/PH

  7. First prototype in the IHP SGB25VGOD technology – main technology chosen after radiation tests of LDMOS (high-V) transistors Design included in MPW run of May09 Features integrated in the prototype: oscillator (with sawtooth) and reliable soft start procedure Improved and safer handling of dead times during commutation (with adaptive logic monitoring the output node). Higher efficiency and softer commutations proven More reliable mechanism for power transistor turn-off to prevent possible multiple commutations in a cycle External components needed Regulated voltage supplies bandgap reference Compensation network Packaged in QFN48 IHP1 prototype 2.8mm 2.5mm S.Michelis CERN/PH

  8. Measurement vs Estimate Vin=10V, Vout=2.5V, Iout=2A Estimated Efficiency S.Michelis CERN/PH

  9. Example of the choice of conditions (L, frequency) for the following requirements: Vin=10V, Iout=1 and 2 A, Vout=2.5 to 0.9V Each point obtained setting L and frequency such that the evaluated efficiency is the highest Using estimate to choose L, f S.Michelis CERN/PH

  10. IHP2 prototype • Second prototype in the IHP SGB25VGOD technology • Design included in MPW run of Jan10 Expected back in May 2010 • Additional features integrated in the prototype: • Linear regulators • Bandgap • Overcurrent protection • Improvement in the adaptive logic • Triplication and logic against SEU • Enablers • Complete circuit • Over current protection • Dimension of the power transistors • External components needed • Compensation network Half power transistor switched off 2.9mm 3mm S.Michelis CERN/PH

  11. Moving from IHP1 to IHP2 S.Michelis CERN/PH

  12. Adaptive logic IL Pmos L Vout Phase Phase IL High side comp Cout Almost zero diode conduction Diode Conduction Nmos Low side comp Negative comp Adaptive logic allows reducing the dead time. This optimizes the switching operation and improves the efficiency Nmos on Pmos on Pmos on Nmos on S.Michelis CERN/PH

  13. Overcurrent protection Pmos Over current limit Over current sensing L Vout Phase IL Cout Nmos IL Turn off Pmos Pmos on • 2 possible cases: • Current limiter during startup • Converter restart after startup Pmos on Nmos on S.Michelis CERN/PH

  14. Bandgap circuit The sensitive part of this design and in this technology is the diode. Different diode layouts with enclosed design, additional guard rings and different current density need to be investigated Bandgap voltage Vs TID with normal diode S.Michelis CERN/PH

  15. Bandgap circuit Different bandgap version in IHP technology has been designed and submitted in October 2009. Expected back this week Target is high stability of the bandgap voltage over variation of temperature, Vdd, TID and displacement damage. Results will be presented soon S.Michelis CERN/PH

  16. Schedule IHP2 • Mid May 2010 • 20 Chip expected back in package QFN48 • May-June 2010 • Extensive functional and radiation tests • July-August 2010 • Order of 100 naked chip • Decision of necessary control pins and packaging in QFN32 IHP3 • Next submission • Investigating bump bonding • Reduction of resistance of on chip metal and bondings • Smaller size if direct bondend on pcb (~3x3 mm) S.Michelis CERN/PH

  17. Conclusion • AMIS2 is a prototype in the backup technology that is fully functional with • TID up to 300Mrd • proton fluence up to 5 1015 p/cm2 • efficiency between 70 and 80% Excellent noise performances of AMIS2, mounted on optimized PCB, will be presented by Georges • ASIC designed in IHP technology has better performances (efficiency between 80 and 85%). A complete design with protection is expected back in May 2010 S.Michelis CERN/PH

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