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Ioannis Parnassos, Panagiotis Skrimponis, Georgios Zindros, Nikolaos Bellas

SoCLog: A Real-Time, Automatically Generated Logging and Profiling Mechanism for FPGA-based Systems On Chip. Ioannis Parnassos, Panagiotis Skrimponis, Georgios Zindros, Nikolaos Bellas. Motivation. What: Need for system-level performance analysis of SoCs

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Ioannis Parnassos, Panagiotis Skrimponis, Georgios Zindros, Nikolaos Bellas

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  1. SoCLog: A Real-Time, Automatically Generated Loggingand Profiling Mechanism for FPGA-based Systems On Chip Ioannis Parnassos, Panagiotis Skrimponis, Georgios Zindros, Nikolaos Bellas

  2. Motivation What: Need for system-level performance analysis of SoCs Why important: Use to evaluate system-level performance and iteratively optimize How: Limited availability of graphical logging/profiling mechanisms at system level to detect performance bottlenecks and improve performance No VTUNE for FPGA SoC exists FPL 2016

  3. SoCLog • SoCLog is a hw/sw infrastructure to automatically generate logging mechanisms in an FPGA-based SoC • Runtime capture and visualization of activity of the components of an SoC • Automatic generation of all hardware component required and easy access of all activity information at the application software level FPL 2016

  4. SoCLog HW Architecture • Sampling and Trigger (S&T) mechanisms used to detect Start/End of a transaction. Added as attachments by SoCLog automatically to • Accelerators • Peripherals • Buses FPL 2016

  5. SoCLog HW Architecture Detect the Beginning and End of each Read Data Channel Transaction Detect the Beginning and End of Accelerator invocation DCT Accelerator S&T Trigger ap_done DCT accelerator ap_start AXI-4 Bus Read Channel S&T BRAM Event Logging Trigger AXI-4 Bus Profile Logic FPL 2016

  6. SoCLog SW Architecture Extends RIFFA 2.0 API intfpga_recv_log (fpga_t *fpga, intchnl, void * data, long timeout) fpga_t * fpga = fpga_open(0); int r = read_data(“input_file", buf, BUF_SIZE); printf("Read %d bytes from file", r); int s = fpga_send(fpga, chnl, buf, BUF_SIZE/4, 0, 1, t); printf("Sent %d words to FPGA", s); r = fpga_recv(fpga, chnl, buf, BUF_SIZE/4, t); printf("Received %d words from FPGA", r); // Process results ... w = fpga_recv_log (fpga, chnl, log_buf, t); // Process log data in log_buf and show in GUI ... fpga_close(fpga); RIFFA (Reusable Integration Framework for FPGA Accelerators) is a simple framework for communicating data from a host CPU to a FPGA via a PCI Express bus. FPL 2016

  7. JPEG application (VIDEO) • SoC with three HW accelerators • DCT • Quantization, inverse Quantization (Q/iQ) • iDCT Unoptimized DCT (839 cycles/block) Optimized iDCT (255 cycles/block) Both DCT/iDCT are optimized FPL 2016

  8. Conclusions • SoCLog a system-level logging/profiling, GUI-based, HW/SW infrastructure for FPGA SoCs • Transparent to the user • Very low area overhead • Can be used to evaluate performance and detect bottlenecks at system level • Incrementally and spirally drive optimization directives at component level FPL 2016

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