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Timing Analysis

Timing Analysis. Chaitanya Bandi. Instructor: Dr. Vishwani D. Agrawal ELEC 7770 Advanced VLSI Design Team Project. Need for Timing Analysis.

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Timing Analysis

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  1. Timing Analysis Chaitanya Bandi Instructor: Dr. Vishwani D. Agrawal ELEC 7770 Advanced VLSI Design Team Project

  2. Need for Timing Analysis • High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. • While timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical.

  3. Primitive device delay models • A primitive logic gate has an intrinsic delay.

  4. Methods of Timing Analysis • Static Timing analysis after Synthesis (Pre-Layout Analysis) • Static Timing analysis after Place and Route (also called as Post-Layout Analysis)

  5. Static Timing Analysis Only two kinds of timing errors are possible in such a system: • A hold time violation, when a signal arrives too early, and advances one clock cycle before it should. • A setup time violation, when a signal arrives too late, and misses the time when it should advance.

  6. Area Optimized Vs Delay Optimized From the Synthesis report of the Area and Delay Optimized versions, the Area Optimized version has lesser Area and Delay compared to the Delay Optimized version.

  7. Tools to perform Timing Analysis • QuickSim • Mach TA • Eldo • Leonardo (Results from the Synthesis)

  8. ELDO Design Flow

  9. Procedure • Extract the schematic from the Netlist. • Export it as a Spice format. • Force vectors to observe the critical path from the simulation results files. • Find the critical path from the Waveform Viewer (EZWAVE)

  10. Leonardo • The Delays from the Area Optimized netlist shows that the CPU design has a critical path that has a delay of 13.13ns • This is just an estimate of the pre-layout timing analysis. This delay may differ based on the level of optimization.

  11. Further Work • The Post layout incorporates both the block and routing delays as a final analysis of the design’s timing constraints. • Post layout simulation is a better parameter to find the maximum operational frequency and behavior of the circuit.

  12. Mach TA Post Layout Design Flow

  13. Questions??

  14. Suggestions • Technology that is supported by the timing analysers. • 32-bit Processor requires simulation of few days to perform the timing and power analysis. A 16-bit processor would have been a better choice.

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