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Evaluation of Actel FPGA Products by JAXA

2005 MAPLD International Conference. Evaluation of Actel FPGA Products by JAXA. Yasuo SAKAIDE 1 , Norio NEMOTO 2 Kimiharu Kariu 1 , Masahiko Midorikawa 1 , Yoshiya Iide 1 , Masakazu Ichikawa 1 , Tamotsu Yokose 1 , Yoshihisa Tsuchiya 1 , Toshifumi Arimitsu 1 ,

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Evaluation of Actel FPGA Products by JAXA

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  1. 2005 MAPLD International Conference Evaluation of Actel FPGA Products by JAXA Yasuo SAKAIDE1, Norio NEMOTO2 Kimiharu Kariu1, Masahiko Midorikawa1, Yoshiya Iide1, Masakazu Ichikawa1, Tamotsu Yokose1, Yoshihisa Tsuchiya1, Toshifumi Arimitsu1, Noriko Yamada2, Hiroyuki Shindou2, Satoshi Kuboyama2, Sumio Matsuda2, and Takashi Tamura2 High-Reliability Components Corporation (HIREC)1 Japan Aerospace Exploration Agency (JAXA)2 1

  2. Test Objectives Failures on programmed anti-fuse of Actel FPGA products which were built in the 0.25 um MEC/Tonami process have been reported in U.S. since 2003. Japan Aerospace Exploration Agency (JAXA) started to evaluate Actel FPGA products; A54SX-A (MEC) and RTSX-SU (UMC) in the end of 2004. -MEC die devices- To determine the acceleration factors of the antifuse failures by performing operational life tests at various temperatures. -UMC die devices- To evaluate the reliability for space applications by performing long-term life tests and radiation tests. 2

  3. Test Item and Conditions Note: MECdevices are programmed with the “old programming algorithm (ver.4.42)”. UMC devices are programmed with the “original programming algorithm (ver.4.48)”. 3

  4. Test Vehicle (1) Evaluation test circuit – Diagram Design features 1- 4-input AND-OR chains:  Maximum utilization of antifuses 2- Stable operation using an external clock circuit:  Easier failure detection 3- R-cells driven by skewed clock:  Delays detectable to less than 10nsec 4- Continuous monitoring of XORed outputs from the same circuit block:  Real-time detection of failures x4:32A/32SU x8:72A 4

  5. Test Vehicle (2) The number of antifuses in test vehicles 5

  6. Test Results (1): Weibull Plots • Weibull plots for 72A samples were successfully obtained and the failure mode was infant mortality. • Weibull plots for 32A samples were slightly different and and statistically poor because of small sample size. 6

  7. Test Results (2):Failure Rate as a Function of Time Failure rates were calculated based on the Weibull plots for 72A samples. The failure rates are consistent with 32A and 72A data within practical application purpose.It was considered that the difference of the failure rate was caused by lot difference because of the same structure of 32A and 72A. 7

  8. Test Results (3):Acceleration Factor Ea=0.002eV Temperature acceleration factor was calculated based on the Weibull plots for 72A samples Given activation energy was too small to screen out the defective antifuses throughtout PPBI (125 deg.C, 240 hours) 8

  9. Conclusions Weibull plots for the antifuse failures of A54SX-A (MEC) FPGAs were successfully obtained. The failure mode was infant mortality. Given temperature acceleration factor was too small to screen out the defective antifuses throughout PPBI (125deg.C 240hours). No defective antifuses were observed for RTSX-SU (UMC) FPGAs. Based on the results, the MEC die FPGAs shall be replaced with UMC ones by decision of JAXA projects. 9

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