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Introduction to IC Design. Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2003/12/01. I/O Structures. Bonding ESD I/O Pad Power Pads Guard Ring, Quiet Ring Tristate and Bidirectional Pads. Packages. Bonding.
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Introduction to IC Design Tsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2003/12/01
I/O Structures • Bonding • ESD • I/O Pad • Power Pads • Guard Ring, Quiet Ring • Tristate and Bidirectional Pads
Bonding Ultrasonic Beam Pad Passivation/overglass
Pad Building Metal-Upmost Via Metal_Underlayer N-Well
ESD Electrostatic Discharge 1.5k CUT 100p Class 4 • ESD Classification: Class 3 Class 2 Class 2 Class 1 1kV 2kV 4kV 8kV 16kV 32kV 64kV • Usually, discharging time ~ 100ns • Input resistance ~ 1K for common ICs. • Test Bench:
Typical ESD Protection V I ~ 40V
Diode Clamper and Protecting Resistor Poly-resistor p-Diff resistor -40 < V < +40 Be careful of RC for Hi-speed!
PAD vs. Core Core Core-Limited Pad-Liimited
Connection between PADs • Butting • Feed-through • Wired Corner pads Core
Rings around the Cores Core Sensitive Core Guard Rings Pad-Power Rings Core-Power Rings Quiet Rings Dirty Rings Clean Rings Diffusion Rings User Rings Usually lowest outer
Miscellaneous Pads • Power Pads: Noise Prevention, Separation • Input Pads: Level-Shifting, Input Protection • Output Pads: Drive, Latch-up Prevention • Clock Pads: RC Reduction • Heat-sink Pads: (connected to) Heat Sink • Stand Pads: (e.g., LCD display) • Scan Pads: with Boundary Scan Cell • Virtual-Ground Pads: with SLEEP Transistor • Register Pads: to reduce tCQ, tDC • Schmitt-Trigger Pads • Pull-Up/Down Pads • Analog/Digital Pads • Dirty/Clean Pads
Latch-up Effect in n-Well Process Vss IN OUT Vdd Latch up ! 正回授鎖死而燒毀!
Guard Rings • Noise Reduction • Latch-up prevention especially for Output (Hi-I) Pads • To guard deeply (under thinox), Diffusion Rings are usually used. • For diffusion rings, Poly-crossovers are inhibited.
Pad-Limited Pads core
Core-Limited Pads core
TTL Input PAD VDD VDD 1:6 IN OUT Wide IN OUT VSS VSS
A Tri-state/Bidirectional Pad OE Din Dout
Sleep Transistor in Pads VSS I/O
Boundary Scan Cell in I/O Pad 0 0 1 1 0 0 1 1 D D D D Q Q Q Q
Homework #3 • Applying an account to use Cadence/Virtuoso • Select or design a circuit with about 2~10 transistors • Inverter, • Transmission gate, • D-Latch • NAND2, NOR2, etc. • Draw the Schematics • Transistor sizing and Pre-layout simulation • Layout using Virtuoso, Laker or L-Edit • DRC, LVS (Dracula or Calibre, at least Diva) • Extract to a SPICE file • Post-layout simulation on the typical function of your circuit. Due to the final-exam day (no postponement). A tutorial can be download from my instruction web.
Simple Tutorial and Tips about HW#3 • X-Windows • Solaris/UNIX • Design Flow
X-Window • X-Windows Tools • eXceed • Xdemo • Xwin32 • Graphic-Base Exchange Protocol • 1990 X11 • Present Unix/Solaris facilities X-windowDaemon; • For PC/Windows, X-window Client Package should be installed.
Usually, Daemon xdm has Installed set DISPLAY 163.23.247.178:0.0 who Run Xwindow client telnet 163.23.247.191 winipcfg 163.23.247.191 cad1.el.ccut.edu.tw 163.23.247.178 Typical Configuration of Xwindow
Daemon xdm Protocol Typical Configuration of Xwindow
Login Shell as a Window in Windows Press User name and Password
(1)右鍵出現選單 (2)由Tools選擇Terminal (4)最後按EXIT離開 (3)有4個桌面可以用 OpenWindows
Typical (Suggested) File/Folder Allocation $home ~ bin TSMC035 tmp work tf check 0.35um技術檔 035.tf divaDRC.rul divaLVS.rul divaLPE.rul drc lvs lpe display.drf cds.lib 色盤設定 線上Diva 的檢查規則 離線Pdracula 的檢查規則 CDS資料庫
Utilizing script and alias • 常要設定 setenv DISPLAY (IP):0.0 • 可以用alias 替代指令被替代的指令串 • 例如: alias d ‘setenv DISPLAY !*\:0.0’ • 在~/.cshrc設定,則login後只要d (IP)即可 • more ~tch/.cshrc • cp ~tch/.cshrc ~ • source cds_0006.cshrc • icfb &
Be careful of the error message frequently. Exit from Cadence by CIW→FILE→Exit as possible! Exit Library Open File New CIW Cell view Tools Library manager New CIW: Command Interpretation Window