Introduction to IC Test

1. Introduction to IC Test Tsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/05/24

2. Introduction to Memory Testing Outline • Basic Concepts about Memory/Storage • Introduction to RAM/ROM Structure • Reduced Functional Memory/Fault Models • RAM Test • ROM Test • IDDQ Test for Memory • Parametric Test • Dynamic Test • Random Test • MBIST

3. Typical Storage Hierarchy FF Register L1 Cache SRAM SRAM DRAM L2 Cache Main Memory DRAM Archive I Magnetic disk Archive II Optical disk

4. Moore’s Law on Transistor Counts

5. Moore’s Law on Memory 1020 bits 1017 bits 1985 2000

6. MOS Memory Learning Curve

7. Taxonomy • by Access Structure • Random Access Memory (RAM) • Serial Access Memory (SAM) • Content Access Memory (CAM) • by Alterability • RAM: R/W Memory, SRAM, DRAM, CCD • ROM • EPROM • EEPROM • Filed Alterable ROM, e.g., Flash • by Device: BJT, NMOS, CMOS, CCD

8. Basic CCD

9. Basic Static RAM (SRAM) Bit Line Bit Line Word Line

10. Basic SRAM Architecture Memory Array Row Address Buffer Row Decoder BL N R N N WL SA Control Column Decoder M M M Column Address Buffer

11. A Simple Sense Amplifier (SA) VDD Bit Bit CS Typically, the SA must be sensitive enough to read about 10mV.

12. Historical Evolution of DRAM Read Select R/W Select Write Write Read Read Write Select R/W Select Read Select Data Data Write Select

13. Historical Evolution of DRAM Basic Planar and Trench DRAM Cells Word Bit Planar Cell Word Bit Trench Cell

14. Basic ROM Architecture Bit Line Word Line

15. Reduced Functional Memory Model C: Cell Array 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 Row Address Decoder D: Data 0 0 1 1 1 1 0 0 Read/Write Logic 0 1 0 0 1 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 Column Address Decoder A: Address

16. Reduction of Functional Faults • Stuck-At Faults • Cell stuck • Driver stuck • Read/write line stuck • Chip-select line stuck • Data line stuck • Open in data line • Transition Faults • Cell can be set to 0 but not to 1 or vice versa. • Coupling Faults • Short between data lines • Crosstalk between data lines • Neighborhood Pattern Sensitive Faults • Pattern sensitive interaction between cells • Address-decoder Faults • Address line stuck • Open in address line • Shorts between address lines • Open decoder • Wrong access • Multiple access

17. Reduced Functional Faults Fault Models • Address Decoder Faults • Memory Cell Faults • Single Cell Faults • Single-Cell Stuck-At Faults (SCSF) • Single-Cell Transition Faults (SCTF) • Dual-Cell Faults • Coupling Faults (CF) • Multiple-Cell Faults • Neighbor Cell Faults • Single Line Faults • Neighbor Line Faults

18. Fault Levels and Assumptions Base cell read & non-transition write operations will not cause an error; transition write operation may cause an error. • Inversion coupling faults • Idempotent coupling faults • Bridging coupling faults • State coupling faults CF NPSF TF SAF

19. Coupling Functional Faults Coupling Relations • Assume w(x, y) denotes a write y operation to a cell containing an x. • <I/F> denotes a fault in a single cell where I describes the sensitizing input and F describes the fault value. • <I1, I2, …, In-1; In/F> denotes a fault involving n cells where I1, I2, …, In-1 describes conditions on the n-1 cells to sensitize the fault in cell n and In describes the condition for the fault to be sensitized in cell n.

20. Coupling Functional Faults A. J. van de Goor, 1991 • Classified by Cell Count k and Affected Position Count p. • r: the corresponding row; c: the corresponding column • n = R x C, the total number of cells.

21. March Test Suk, 1981 • A march test consists of a finite sequence of march element that is a finite sequence of operations applied to every cell in memory before proceeding to the next cell. • Notation of March Tests:

22. March Test Suk, 1981 • Operations of March Tests: • w0: write zero to the cell, • w1: write one to the cell, • r0: read and detect whether the result is 0, • r1: read and detect whether the result is 1. • Example: the simplest model (non-coupling SAF) • For the non-coupling SAF, 2n wr-operations are needed.

23. Traditional RAM Test • Zero-One: • Not all TF, CF are detected, 4x2a length (a-bit address) • Checkboard: • additionally detects shorts btw adjacent cells. • GALPAT (Galloping pattern) and Walking 1/0 • Sliding Diagonal • Butterfly

24. Multiple RAM Fault March Tests • Test-US: MATS, MATS+ • Modified Algo. Test Seq. for unlinked SAFs. • Test-UT: Marching 1/0, • MATS++ • Test-UCin: March X • Test-UCid: March C- (C) • Test-LCid: March A • Test-LTin: March Y • Test-LTCid: March B

25. Comparison on Fault Coverage

26. Memroy BIST Architecture Centralized Distributed CUT TPG CUT ORA Separate DIST DIST TPG ORA CUT TPG CUT ORA BISTC Embedded Microprocessor based BIST is possible for SoC Test. TPG: Test Pattern Generator, ORA: Output Result Analyzer CUT: Circuit under Test, BISTC: BIST Controller

27. Schmoo Plot Worked parameter2 Failed Lack parameter1 • To show the parametric relations during parameter test.

28. Concurrent Test and Partitioning • Partitioning is frequently used to reduce the power dissipation, time response and to provide possible concurrency for most circuits. • Generic Memory Partitioning:

29. RAM Self-Repair 2c columns spare columns 2r rows spare rows • To promote the product yield.

30. IDDQ Testing Basic Concept IDD IDD VDD IDD t t Current Sensor

31. Classification of Random Test for RAMs RAM A SA W D DDDDRRRR DDRRDDRR DRDRDRDR D: Deterministic R: Random

32. PRPG and SISR/MISR (reviews) Cn=1 Dn + + + + + C2 C1 C4 C3 Cn-1 D1 D3 D2 D4 Dn-1 Reset all FFs

33. Introduction to ROM Tests • In Logical ROM Test, only read operations are concerned. • However, production tests for PROMs and EPROMs are concerned with ascertaining that the device can contain any data that may need some specialized tests. • Most RAM test algorithms can be used/modified for ROMs. • Useful Test Methods: • Parity Checking • Checksum (e.g., JEDEC standards) • Cyclic Redundancy Checking (CRC) (e.g., using LFSR)

34. Introduction to Dynamic Tests • Dynamic faults are electrical faults the causes of which are time dependent and internal to the chip. • Classification of Dynamic Faults: • Recovery Faults • Sense Amplifier Recovery (SAR) • Write Recovery (WR) • Retention Faults • Sleeping sickness • Refresh line stuck at • Static data loss • Imbalance Faults • Bit-line precharge voltage imbalance fault • To test dynamic faults, the characteristics of most algorithms are to repeat some operations for many times.