1 / 15

Introduction to IC Test

Introduction to IC Test. Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/03/29. Syllabus & Chapter Precedence. Introduction. Modeling. Logic Simulation. Fault Modeling. Fault Simulation.

rlynch
Download Presentation

Introduction to IC Test

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Introduction to IC Test Tsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/03/29

  2. Syllabus & Chapter Precedence Introduction Modeling Logic Simulation Fault Modeling Fault Simulation Testing for Single Stuck Faults Design for Testability Test Compression Built-In Self-Test (I)

  3. Related to Faults • System Failure: System doesn't work. • Error: Incorrect operation of a system, that possibly works. • Design errors • Physical Faults • Physical Fault: incorrect operation of a modeled element due to Fab. • Fabrication errors • Wrong components • Incorrect wiring or shorts • Physical Defects • Classified according to time stability: • Permanent • Intermittent • Transient • Physical Defect: • Fabrication defects • Physical failure

  4. Physical Faults • Logical Faults: the effect of physical fault on the behavior of the modeled system. • Faults that affect the objective function • Delay faults • Modeling physical faults to logical faults: • Complexity reduction • Technology-independent • Tests may be used even if behavior unknown • Views: • Structural faults • (Wire, transistor) Short/open • Stuck-at • Bridging fault • Functional faults • Simultaneous occurrence: • Single-fault assumption • Multiple-fault

  5. Inductive Fault Analysis N Well Investigate what and how more physical faults induce to high-level faults.

  6. Fault Detection of Combinational Circuits Combinational Network N Faulty Network Nf with a fault f

  7. Test Vector 0 0 1 1 1 0 * 1 1 1 1 • A test (vector) t detects a fault fZf(t)≠Z(t). • Example: a fault with a component error

  8. Sensitization A F I Hi 1 B H 0 0/1 J Hj 0 1 C L G K D f E Sensitized path • A line whose value in the test t changes in the presence of the fault f is said to be sensitized to the fault f by the test t. • Example: C17 in ISCAS85 benchmark

  9. Detectability & Redundancy • A fault f is said to be detectable if there exists a test t that detectf; otherwise, undetectable. • A combinational circuit that contains an undetectable stuck fault is said to be redundant, since such a circuit can always be simplified by removing at least one gate or gate input. • Trivially (directly) redundant gate (input):

  10. Detectability & Redundancy Ckt Ckt M Ckt • Some meaningful redundant circuits: • TMR (Triple modular redundancy) for fault-tolerant design. • Hazard masking gate • Dummy circuits for matching or cancellation.

  11. Practically Undetectable • Redundancy identifying ~ test generation : NP-complete! • NP-complete: a problem is said to be NP-complete if no polynomial-time algorithm exists. • (Usually it can be solved in polynomial-time for most instances, but at least one instance needs exponential time.) • In a practical sense, there is no difference btw an undetectable fault and a detectable one that is not detected by an applied test set. • To have a fair test efficiency for a test tool, the definition of the redundant faults (circuits) should be cared.

  12. Fault Equivalence x z y • Two faults f and g are said to be functionally equivalent (under all possible inputs x E X) Zf(x)=Zg(x). • For any t, Zf(t)≠Zg(t)  f and g are distinguishable. • For fault analysis it is sufficient to consider only one reprehensive fault from every equivalency class. • For a gate with controlling value c and inversion i, all the input s-a-c faults and the output s-a-(c^i) are functionally equivalent. • Equivalence Fault collapsing: Reduction of faults required to analyze based on equivlance.

  13. Fault Dominance A Z B • Let Tg be the set of all tests that detect a fault g. • F dominates g Zf(Tg)=Zg(Tg). Dominant Equivlent • For a gate with controlling value c and inversion i, the output s-a-(!c^i) dominates any input s-a-!c. • Dominance Fault collapsing: Reduction of faults required to analyze based on dominance.

  14. Fault Detection of Sequential Circuits Combinational Network N Faulty Network Nf with a fault f

  15. Fault Detection of Sequential Circuits Single Clock, Synchronous, DFF-based PI: Primary Inputs PO: Primary Outputs N Z X Combinational Circuit L PPI: Pseudo PI PPO: Pseudo PO Q D M M y Q Q Q Q D D D D Y PS: Present State NS: Next State Clk Initialization sequence Initial State So

More Related