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Technology Migration Technique for Designs with Strong RET-driven Layout Restrictions

Technology Migration Technique for Designs with Strong RET-driven Layout Restrictions. Xin Yuan, Kevin McCullen, Fook-Luen Heng, Robert Walker, Jason Hibbeler, Robert Allen, Rani Narayan April 5, 2005. Outline. Introduction Review related work Our solution Experimental Results

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Technology Migration Technique for Designs with Strong RET-driven Layout Restrictions

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  1. Technology Migration Technique for Designs with Strong RET-driven Layout Restrictions Xin Yuan, Kevin McCullen, Fook-Luen Heng, Robert Walker, Jason Hibbeler, Robert Allen, Rani Narayan April 5, 2005 ISPD 2005

  2. Outline • Introduction • Review related work • Our solution • Experimental Results • Conclusion and ongoing work ISPD 2005

  3. Coarse grid dummy polysilicon Restrictive Design Rules (RDRs)[Liebmann et al SPIE 2004] • Strong Resolution Enhancement Technique (RET)-driven design rules • Require: • Limited number of narrow linewidths • Single orientation of narrow features • Narrow features placed on uniform and coarse pitch • Uniform proximity environment for all critical gates • Limited number of pitches for critical gates ISPD 2005

  4. CA to RX space increased CA to RX space increased spacing and width are squeezed to minimum Poly Non min spacing and width are preserved Tight neighbors are perturbed as needed CA to RX space violation M1 Diffusion Minimally perturbed layout with design rule violation removed compacted layout using min area and wirelength objective min M1 space Contact Layout with design rule violation in new technology Minimum Layout Perturbation (MinPert)-based Design Migration • Design migration: key to achieve maximum layout productivity • MinPert [Heng et al ISPD97]: fix all the design rule violations with minimum total perturbation of the layout • Conventional migration techniques target for area and wirelength minimization (a.k.a. layout compaction) ISPD 2005

  5. dij diffusion Constraint graph G=(V,A), Linear constraint set Vj Vi poly Ground rule: diffusion overlap past poly bydij Vj(X) - Vi(X)  dij Vi Vj • Location perturbation objective (LocPert): • Linear programming problem formulation Minimum Layout Perturbation (MinPert)-based Legalization • Constraint-based legalization • Model layout rules constraints into a constraint graph G=(V, A) • layout element Ei  Node Vi V • Rule constraints between layout elements  arcs between nodes ISPD 2005

  6. Minimum Layout Perturbation-based Design Migration for RDR constraints (MPRDR) • Challenges: • Discrete space constraints (grid constraints) • A brand new problem, nobody studied it before • It is a mixed integer linear programming (MILP) problem • Not practical to use MILP solver • Compaction with grid constraints was solved in 1987 by J. F. Lee et al • Different objective and not applicable • Our solution is an enhancement to the minimum layout perturbation-based technology migration technique proposed in 1997 ISPD 2005

  7. 3 1 5 7 4 2 6 ARDRs ARDRns Minimum Layout Perturbation-based Design Migration for RDR constraints (MPRDR) Problem Formulation • Given constraint graph with out RDR constraint G=(V, A) of a layout, build augmented constraint graph G’ =(V, AARDRsARDRns) • Relax it to mixed integer linear programming problem (MILP) ISPD 2005

  8. v11 V4 v8 2 1 1 1 2 v2 2 2 1 v12 1 v14 2 v9 v6 2 v15 v1 1 1 2 v3 1 2 v16 v7 v13 1 1 1 v10 v5 Our Solution: A two-stage Approach • Stage 1: Compute the target grid position of gates to meet the grid constraints with MinPert flavor • model gates and their neighborhood relationship as a directed graph called PC neighborhood graph (PCN-graph) • Minimum perturbation-oriented placement algorithm PCSP to “place” nodes (gates) on pitch based on the PCN graph ISPD 2005

  9. Left boundary Linear constraint to target location Our Solution: A two-stage Approach • Stage 2: Treat the target grid positions of gates as design rules to be fixed by the minimum perturbation optimization • For each gate Eig, given the target on-pitch location computed by PC placement algorithm T(Eig) wrt the cell left boundary position, denoted as Vlf(X), convert RDR constraints to a set of space constraint between the left boundary and the gates ISPD 2005

  10. v11 V4 v8 2 1 1 1 2 v2 2 2 1 v12 1 v14 2 v9 v6 2 v15 0 v1 1 1 2 v3 s 1 2 v16 v7 v13 1 0 1 1 t v10 v5 PCN-Graph ISPD 2005

  11. PC Shape Placement (PCSP): Algorithm Overview PCN-graph • Estimate the range of possible valid grid positions of each node • analyze the slack of target position based on PCN-graph • Estimate the minimum width of the layout in terms of grids Place nodes with the least slack in topological order within their valid position range and close to the original positions as much as possible Update valid grid position and slack for unplaced nodes end ISPD 2005

  12. v11 ,12 12 V4 ,4 4 ,10 v8 10 ,2 2 2 v2 2 1 1 1 2 1 v12 ,14 14 2 v14 17 ,17 v9 v6 1 6 ,6 2 ,0 ,18 18 0 v15 v1 2 1 ,0 1 0 2 2 v3 1 ,19 v16 19 v7 v13 ,19 0 19 1 1 ,11 11 1 0 s t ,3 3 8 ,8 16 ,16 v10 v5 ,5 4 12 ,13 Compute Slack on PCN-graph • Topological sorting on PCN-graph, {s, v1, v2, v3, v4, v5, v6 ,v7, v8, v9, v11, v10, v12, v13, v14, v15, v16,t} • left(s)=0 , position source node at grid position of 0 • Visit node vj in topological order, • left(vj) = max {left(vi)+ w(eij) }, for all eij • Min_W = left(t), right(t) = max{target_W, min_W} , let w0 be the width of the given layout, scaler=right(t) / w0, for each node vi, old(vi) = old(vi)*scaler. • Visit node vi in reversed topological order, • right(vi) = min {right(vj)- w(eij) }, for all eij • slack(vj) = right(vj)– left(vj), ISPD 2005

  13. PC Shape Placement (PCSP): Algorithm Overview PCN-graph • Estimate the range of possible valid grid positions of each node • analyze the slack of target position based on PCN-graph • Estimate the minimum width of the layout in terms of grids Place nodes with the least slack in topological order within their valid position range and close to the original positions as much as possible Update valid grid position and slack for unplaced nodes end ISPD 2005

  14. Experimental Results • PC Shape Placement vs GLPK (a MILP solver) to solve Problem (4) in the first stage ISPD 2005

  15. Experimental Result (con’t) After legalization Before legalization ISPD 2005

  16. Conclusion and Ongoing Work • Study the problem of MPRDR • Propose a two-stage approach to solve the MILP problem • Propose the heuristic algorithm to compute target on-grid locations with minPert flavor • Our solution works well on industrial layouts • Ongoing works • Handle hierarchical design • Handle grid constraints on other layout objects ISPD 2005

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