Simultaneous Layout Migration and Decomposition for Double Patterning Technology

1. Simultaneous Layout Migration and Decompositionfor Double Patterning Technology Chin-Hsiung Hsu, Yao-Wen Chang, and SaniRechardNassif From ICCAD09

2. Outline • INTRODUCTION • PROBLEM FORMULATION • SIMULTANEOUS LAYOUT MIGRATION AND DECOMPOSITION FLOW • Potential DPT-Conflict Graphs and Pattern Splitting • DPT-aware Constraint Graphs • Basic ILP Formulation • ILP Problem-Size Reduction • DPT-aware Standard Cells • EXPERIMENTAL RESULTS

3. INTRODUCTION • Double patterning technology (DPT) and layout migration (LM) are crucial technologies for chip manufacturing in the nanometer era. • Due to their interplay, it is necessary to consider the effects of the two technologies simultaneously to obtain a better design flow for manufacturability enhancement.

4. Sub-pattern geometric closeness

5. Outline • INTRODUCTION • PROBLEM FORMULATION • SIMULTANEOUS LAYOUT MIGRATION AND DECOMPOSITION FLOW • Potential DPT-Conflict Graphs and Pattern Splitting • DPT-aware Constraint Graphs • Basic ILP Formulation • ILP Problem-Size Reduction • DPT-aware Standard Cells • EXPERIMENTAL RESULTS

6. PROBLEM FORMULATION( SMD problem) • Input: original layout L ,double-patterning spacing Sd minimum overlap length lo for splitting patterns • Output: decomposed and migrated layout L* • Objective: minimize # of stitch ,area of layout and the sub-pattern geometric closeness • Constraint: design rule constraints ,DPT constraints and minimum-overlap-length constraints.

7. Outline • INTRODUCTION • PROBLEM FORMULATION • SIMULTANEOUS LAYOUT MIGRATION AND DECOMPOSITION FLOW • Potential DPT-Conflict Graphs and Pattern Splitting • DPT-aware Constraint Graphs • Basic ILP Formulation • ILP Problem-Size Reduction • DPT-aware Standard Cells • EXPERIMENTAL RESULTS

8. SIMULTANEOUS LAYOUT MIGRATION AND DECOMPOSITION FLOW

9. Potential DPT-ConflictGraphs and Pattern Splitting • In traditional DPT-conflict graph, a node is introduced to represent a tile, and two tiles are connected by an edge if their spacing is smaller than Sd. Not suitable for this SMD problem

10. Potential DPT-Conflict Graphs and Pattern Splitting • This paper construct an edge between two adjacent tiles even if their spacing is larger than Sd.

11. DPT-aware Constraint Graphs • General edges • Inter-layer constraint • (ex: a contact is covered by a metal) • Intra-layer constraint • (ex: the minimum width and minimum spacing) • DPT-aware minimum-overlap-length constraints • (ex: two tile should overlap with each other for a certain length at the junction for a stitch) • Optional edges • (two tiles can be separated along either the x- or y-direction and at least one separation constraint is satisfied) • DPT edges • (If two tiles are connected by a DPT edge, their spacing needs be at least Sd only if they are on the same mask)

12. Basic ILP Formulation Boundary constraints DRC constraints Stitch constraints DPT constraints

13. A A D B B D C d2 d1 C Horizontal Constraint Graph

14. Stitch

15. ds Distance(ti,tj)<=ds

16. Linearization <=0 = 0

17. Linearization

18. Linearization

19. ILP Problem-Size Reduction If a tile is connected and can be pseudo-colored with a different color without inducing a stitch, the tile and the connecting edge are included into the subgraph.

20. reduces the ILP variables by 44.7%, the ILP constraints by 58.2%, and the DPT edges by 79.9% on average ILP Problem-Size Reduction

21. DPT-aware Standard Cells

22. DPT-aware Standard Cells

23. Outline • INTRODUCTION • PROBLEM FORMULATION • SIMULTANEOUS LAYOUT MIGRATION AND DECOMPOSITION FLOW • Potential DPT-Conflict Graphs and Pattern Splitting • DPT-aware Constraint Graphs • Basic ILP Formulation • ILP Problem-Size Reduction • DPT-aware Standard Cells • EXPERIMENTAL RESULTS

24. EXPERIMENTAL RESULTS Testcases form UMC 90nm Free library and two artificial cases Testing process is 32nm DPT spacing is 64nm(112nm) for poly(metal)

25. EXPERIMENTAL RESULTS