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Applied VLSI design – Phase 1

Applied VLSI design – Phase 1. Martin Kittel Sebastian Stieber. Our design. Multiplier: 17 x 22 bit Pezaris array multiplier 22 bit signed coefficients 16 bit unsigned pixel value + 1 sign bit (‘0‘) Adder: 39 bit ripple carry adder 1 halfadder 38 fulladder. Multiplier.

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Applied VLSI design – Phase 1

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  1. Applied VLSI design – Phase 1 Martin Kittel Sebastian Stieber

  2. Our design • Multiplier: • 17 x 22 bit Pezaris array multiplier • 22 bit signed coefficients • 16 bit unsigned pixel value + 1 sign bit (‘0‘) • Adder: • 39 bit ripple carry adder • 1 halfadder • 38 fulladder

  3. Multiplier [Quelle: J. Stohmann, E. Barke: A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs]

  4. Results • Area: • 3203 • Frequency: • 63,115 MHz • Error: • 0,5155633 • Metric: • 921,58

  5. Drawbacks • Shortened coefficients to 17 bit – for smaller multiplier • Error increases (above 1.0) • Shortened ripple carry adder – 20 bit • Error increases by 0.04 • Area increasesby 200 • Speedup: 400 kHz • => Metric increases by 40

  6. Outlook • Reduce parallel structures • Use only one multiplier and one adder • Reduce adders in offset calculation • Use only one halfadder instead of a 39 bit ripple carry

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