StaticRoute : A novel router for the dynamic partial reconfiguration of FPGAs

1. StaticRoute: A novel router forthe dynamicpartialreconfiguration of FPGAs Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt 2/9/2013

2. Dynamic partial reconfiguration (DPR) M3 M3 M1 M1 M2 M2 • Advantages: • Smaller area • Lower power usage • Disadvantage: • Reconfiguration time • Goal: area reduction with reduced reconfiguration time

3. Conventional DPR tool flow • Different circuits are implemented independently • Complete area is rewritten  Problem: long reconfiguration times

4. Static vs dynamic bits After implementation: • Each memory cell corresponds to a collection of bit values • This collection of bit values is called • a static bit,when the values are the same for all circuits • a dynamic bit, otherwise

5. Clustering of dynamic bits • Only memory cells that contain a dynamic bit need to be rewritten during run-time • Configuration memory of an FPGA is frame-based • Dynamic bits are scattered over the frames • Approach in this work: • Divide configuration frames into dynamic and static ones • Cluster dynamic bits into the dynamic frames

6. CLBs vs routing • In our experiments: • 10% of the configuration memory consists of CLB bits • 90% of the configuration memory consists of routing bits Most of the time spent in reconfiguring the routing infrastructure • Focus on reducing reconfiguration time of routing • All CLB frames are dynamic • Routing frames are divided in static and dynamic ones • Novel router, called StaticRoute, that clusters dynamic routing bits in the dynamic routing frames

7. Proposed DPR tool flow

8. PathFinder • Makes use of a routing resource graph (RRG): directed graph where nodes represent wires and edges represent routing switches • For each net PathFinder finds a minimum cost tree in the RRG • In a first iteration nets are allowed to share resources, i.e. wire congestion is allowed • Negotiated congestion • Cost function of a node in the RRG:

9. StaticRoute • Extended Pathfinder algorithm that also clusters dynamic routing bits into dynamic routing frames • Makes use of an extended routing resource graph (eRRG): • switches are also represented by nodes • mark switches as static/dynamic • keep information about the switches during routing • Detecting dynamic bits • After routing: easy • During routing: not obvious

10. Detecting dynamic bits In general, in the extended RRG, a switch node S connectstwowirenodes Winand Wout. Let usassumethat S is usedby a set of circuits CS . Winand Wout are usedbyCinand Coutrespectively. We state that S is controlledby a dynamic bit if: ((CS ̸=Cin)∨(CS ̸=Cout))∧CS ̸=φ.

11. Novel cost function StaticRoute • Switch congestion: when a static switch is controlled by a dynamic bit • StaticRoute iterates until both wire and switch congestion are resolved • Novel cost function:

12. Experiments • Regular expression matching, adaptive filtering, general MCNC and MCNC20 benchmarks • 200-1500 LBs • Considered only 2 circuits at a time • Comparison of conventional DPR and new flow that uses StaticRoute • Metrics: • Reconfiguration time • Wire length (of each circuit separately)

13. Results – Reconfiguration time

14. Results – Reconfiguration time

15. Results – Wire length

16. Conclusions • Possible to detect dynamic bits during routing • Introduced notion of switch congestion • Novel router, called StaticRoute, that resolves both wire and switch congestion • Using novel DPR tool flow that uses StaticRoute: • Total reconfiguration speed-up of approx. 2X • Increase in wire length is limited

17. StaticRoute: A novel router for the dynamicpartialreconfigurationof Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt 2/9/2013