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Kaijie Wu Polytechnic University kwu03@utopia.poly

Mitigation of Single Event Upset (SEU) by Virtual Redundancy in Design. Paper No. E3. Kaijie Wu Polytechnic University kwu03@utopia.poly.edu Jake Karrfalt Alternative System Concepts, Inc jake@ascinc.com This work is supported by: BMDO (contract # DASG60-01-C-0073) ,

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Kaijie Wu Polytechnic University kwu03@utopia.poly

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  1. Mitigation of Single Event Upset (SEU) by Virtual Redundancy in Design Paper No. E3 Kaijie Wu Polytechnic University kwu03@utopia.poly.edu Jake Karrfalt Alternative System Concepts, Inc jake@ascinc.com This work is supported by: BMDO (contract # DASG60-01-C-0073), JHU Applied Physics Laboratory, Atmel and ASC Wu, Karrfalt

  2. A CED technique that uses the virtual redundancy in design will be presented and a case study is discussed. Purpose Wu, Karrfalt

  3. Describe the idle cycles based CED technique. Describe the RC6 encryption algorithm Implement RC6 encryption data path using the idle cycles based CED. Outline Wu, Karrfalt

  4. A1 A2 A3 M1 M2 M3 C1 C2 C3 C4 × C5 Check Board of idle cycles The idea of idle cycles based CED: +1 +1 A1 A1 +4 +2 +3 +4 +2 +3 A2 A1 A3 A2 A1 A3 +3 +3 *1 *1 M1 A3 A2 M1 *4 *2 *3 *4 *2 *3 M2 M1 M3 M2 M1 M3 *5 *3 *3 *5 M2 M3 M1 M1 Non-CED design CED design Wu, Karrfalt

  5. Symmetric Block Cipher Structure User Key Key Schedule Round Key Encryption Decryption Cipher Text Plain Text Plain Text … … Round 1 Round 1 Round N Round N Wu, Karrfalt

  6. RC6 Encryption Algorithm Input: 128-bit plain text stored in four, 32-bit registers A,B,C,D round keys S[0], S[1], S[2], .., S[43] Output: 128-bit cipher text stored in A,B,C,D B = B + S[0]; D = D + S[1] --pre whitening for i = 1 to 20 do --whitening { t = (B*(2B+1)) <<< 5; u = (D*(2D+1)) <<< 5; A = ((A xor t) <<< u) + S[2i]; C = ((C xor u) <<< t) + S[2i +1]; (A, B, C, D) = (B, C, D, A) } A = A + S[2r+2]; C = C + S[2r+3]; --post whitening Wu, Karrfalt

  7.  + + <<< <<< + + Implementation of RC6 round operation B D   C A <<<5 <<<5 <<<5 XOR XOR <<<5 <<< S(2r) <<< S(2r+1) + + C A Wu, Karrfalt

  8. Data path of RC6 encryption algorithm input + × × <<< + Register Register Register + × × <<< + keys keys C0, C41 C1, C3, … C39 C2, C4, … C40 20 rounds Wu, Karrfalt

  9. M1 M2 O1 O2 × × C1 C2 <<+ <<+ × × C3 C4 <<+ <<+ × × C5 C6 <<+ <<+ Idle cycles of RC6 data path M1 M2 O1 O2 × × C1 × × C2 <<+ <<+ × × C3 <<+ <<+ × × C4 <<+ <<+ × × C5 <<+ <<+ × × C6 <<+ <<+ Wu, Karrfalt

  10. CED data path of RC6 encryption c Register Register input + × × << + Register Register Register + × × << + key key C0, C41 C1, C3, … C39 C2, C4, … C40 20 rounds Wu, Karrfalt

  11. OR AND Fault Injection input input Fault Injection Control Bit Fault Injection Control Bit Component Component Output Output Inject stuck-at-1 fault Inject stuck-at-1 fault Wu, Karrfalt

  12. Fault injection study Clock Fault in input register Result of computation 3 2 Result of recomputation 1 Error Indication Wu, Karrfalt

  13. Fault simulation result Wu, Karrfalt

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