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CSC Synchronization Procedure and Plans

CSC Synchronization Procedure and Plans. Updated July 29, 2005 Jay Hauser / David Matlock / Yangheng Zheng University of California, Los Angeles Martin Von der Mey Fermilab. What is done now What should be done. Overview: Step I, without needing L1A.

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CSC Synchronization Procedure and Plans

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  1. CSC Synchronization Procedure and Plans Updated July 29, 2005 Jay Hauser / David Matlock / Yangheng Zheng University of California, Los Angeles Martin Von der Mey Fermilab What is done now What should be done

  2. Overview: Step I, without needing L1A • Make sure to disable interaction between different TMB/DMB setups in one peripheral crate. Allow only 1 chamber to trigger. • Adjust transmit/receive phases on the TMB for CFEB and ALCT within 25ns base period to get proper data transmission between boards. • Adjust ALCT delay to bring it into coincidence with CLCT • Preliminary check of LCT winner bits returned from MPC to TMB. Slice Test at CERN

  3. Overview: Step II: adjusting LCT-to-L1A timing to 2.900 us required by CFEBs • Adjust LCT or L1A delays to get fixed 2.9us between LCT pretriggers and L1As as seen on the CFEBs. Slice Test at CERN

  4. Overview: Step III, with L1A but not DAQ • Adjust ALCT-L1A coincidence to get ALCT to send ALCT readout data block  TMB(passthrough)  DMB • Adjust CLCT/TMB-L1A coincidence to get TMB to send its readout data block  DMB Slice Test at CERN

  5. Overview: Step IV, getting data read out into DMB FIFOs with L1A gating • Adjust delayed CFEB, ALCT, CLCT Data AVailable (DAV) bits to be in coincidence with L1A on the DMB to get data blocks read into DMB memory (FIFO chips). • Find the trigger data in the output record to verify. Slice Test at CERN

  6. Overview: Step V, with L1A and DAQ readout working • Equalize BX numbers between ALCT, TMB, and CFEBs within a chamber for DAQ readout. • For different chambers in the same peripheral crate use TMB output delay registers to equalize LCT times at the SP. • Equalize time of arrival of LCT signals from different crates at SP. Can do this either with TMB output delays or SP input delays. • Equalize BX numbers between chambers in DAQ readout. Slice Test at CERN

  7. Overview: Step VI, only done with LHC Operation • Adjust ALCT fine delay timing (in 2ns steps) to get events in ~1 bx at SP (for synchronous or semi-synchronous beam) • Overall offset to all BX numbers to make them agree with LHC-defined BX numbers. Slice Test at CERN

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