CPSC 614:Graduate Computer Architecture Memory System II

1. CPSC 614:Graduate Computer ArchitectureMemory System II Based on lectures by Prof. David Culler Prof. David Patterson UC Berkeley

2. Virtual Memory

3. Terminology • Page: a virtual memory block • Page fault: a virtual memory miss • Memory mapping (memory translation): converting a virtual memory produced by the CPU to a physical address

4. Mapping of Virtual Memory to Physical Memory

5. Typical Parameter Ranges

6. Design Issues • A page fault takes millions of cycles to process. • Pages should be large enough to amortize the high access time. (4KB ~ 64KB) • Fully associative placement of pages is used. • Page faults can be handled in software. • Write-back (Write-through scheme does not work.)

7. Where to Place a Page and How to Find it • Fully associative placement • A page table is used to located pages. • Resides in memory • Indexed with the page number from the virtual address and contains the corresponding physical page number. • Each program has its own page table. • To indicate the location of the page table in memory, the page table register is used. • A valid bit in each entry (off: the page is not in memory => page fault)

8. Translation of Virtual Address

9. Page Table Virtual page

10. Writes in Virtual Memory • Writes to the next level of memory hierarchy (disk) take millions of cycles. • Write-through (with write buffer) is not practical. • Write-back (copy back): Virtual memory systems perform the individual writes into the page in memory and copy the page back to disk when it is replaced. • Dirty bit: indicates the page has been modified.

11. TLB (Translation Lookaside Buffer) • Each memory access by a program takes at least twice as long. • One to obtain the physical address in the page table • One to get the data • TLB (Translation Lookaside Buffer) • A cache that holds only page table mapping • Includes the reference bit, the dirty bit, and the valid bit. • We don’t need to access the page table on every reference.

12. TLB Structure Dirty Valid Ref Virtual Page # Physical Page #

13. TLB Acting as a Cache on Page Table

14. TLB Design Issues • When a TLB entry is replaced, we need to copy the reference and dirty bits back to the page table entry. • Write-back (due to small miss rate) • Fully associative mapping (due to small TLB) • If larger TLBs are used, no or small associativity can be used. • Randomly choose an entry to replace.

15. Alpha 21264 Data TLB PID

16. MIPS R2000 TLB Virtual address

17. Memory Hierarchy Processor First-level Cache TLB Second-level Cache address blocks Page Table Memory pages Disk

18. Caches and Memory Systems II:

19. Improving Cache Performance 1. Reduce the miss rate, 2. Reduce the miss penalty, or 3. Reduce the time to hit in the cache.

20. 1. Fast Hit times via Small and Simple Caches • Why Alpha 21164 has 8KB Instruction and 8KB data cache + 96KB second level cache? • Small data cache and clock rate • L1 cache matched to clock rate • L2… caches do not need to match clock rate • Direct Mapped, on chip • On-chip cache avoids large off-chip delay • Same reason for on-chip cache in Intel Xeon processors

21. 2. Fast Hits by Avoiding Address Translation CPU CPU CPU VA VA VA VA Tags PA Tags $ TB $ TB VA PA PA L2 $ TB $ MEM PA PA MEM MEM Overlap $ access with VA translation: requires $ index to remain invariant across translation Conventional Organization Virtually Addressed Cache Translate only on miss Synonym Problem

22. Problem: Flushes on Context Switch • Send virtual address to cache? Called Virtually Addressed Cacheor just Virtual Cache vs. Physical Cache • Every time process is switched logically must flush the cache; otherwise get false hits • Cost is time to flush + “compulsory” misses from empty cache • But still have aliases(sometimes called synonyms); Two different virtual addresses map to same physical address • I/O must interact with cache, so need virtual address • Solution to aliases • HW guarantees covers index field & direct mapped, they must be unique;called page coloring • Solution to cache flush • Addprocess identifier tagthat identifies process as well as address within process: can’t get a hit if wrong process

23. 2. Fast Cache Hits by Avoiding Translation: Process ID Impact • Black is uniprocess • Light Gray is multiprocess when flush cache • Dark Gray is multiprocess when use Process ID tag • Y axis: Miss Rates up to 20% • X axis: Cache size from 2 KB to 1024 KB

24. 2. Fast Cache Hits by Avoiding Translation: Index with Physical Portion of Address • If index is physical part of address, can start tag access in parallel with translation so that can compare to physical tagLimits cache to page size: what if want bigger caches and uses same trick? • Higher associativity moves barrier to right • Page coloring

25. 3. Fast Hit Times Via Pipelined Writes • Pipeline Tag Check and Update Cache as separate stages; current write tag check & previous write cache update • Only STORES in the pipeline; empty during a missStore r2, (r1) Check r1Add --Sub --Store r4, (r3) M[r1]<-r2& check r3 • In shade is “Delayed Write Buffer”; must be checked on reads; either complete write or read from buffer

26. 4. Fast Writes on Misses Via Small Subblocks • If most writes are 1 word, subblock size is 1 word, & write through then always write subblock & tag immediately • Tag match and valid bit already set: Writing the block was proper, & nothing lost by setting valid bit on again. • Tag match and valid bit not set: The tag match means that this is the proper block; writing the data into the subblock makes it appropriate to turn the valid bit on. • Tag mismatch: This is a miss and will modify the data portion of the block. Since write-through cache, no harm was done; memory still has an up-to-date copy of the old value. Only the tag to the address of the write and the valid bits of the other subblock need be changed because the valid bit for this subblock has already been set • Doesn’t work with write back due to last case

27. 5: Fast Hits by pipelining CacheCase Study: MIPS R4000 • 8 Stage Pipeline: • IF–first half of fetching of instruction; PC selection happens here as well as initiation of instruction cache access. • IS–second half of access to instruction cache. • RF–instruction decode and register fetch, hazard checking and also instruction cache hit detection. • EX–execution, which includes effective address calculation, ALU operation, and branch target computation and condition evaluation. • DF–data fetch, first half of access to data cache. • DS–second half of access to data cache. • TC–tag check, determine whether the data cache access hit. • WB–write back for loads and register-register operations. • What is impact on Load delay? • Need 2 instructions between a load and its use!

28. Case Study: MIPS R4000 IF IS IF RF IS IF EX RF IS IF DF EX RF IS IF DS DF EX RF IS IF TC DS DF EX RF IS IF WB TC DS DF EX RF IS IF TWO Cycle Load Latency IF IS IF RF IS IF EX RF IS IF DF EX RF IS IF DS DF EX RF IS IF TC DS DF EX RF IS IF WB TC DS DF EX RF IS IF THREE Cycle Branch Latency (conditions evaluated during EX phase) Delay slot plus two stalls Branch likely cancels delay slot if not taken

29. Alpha 21064 • Separate Instr & Data TLB & Caches • TLBs fully associative • TLB updates in SW(“Priv Arch Libr”) • Caches 8KB direct mapped, write thru • Critical 8 bytes first • Prefetch instr. stream buffer • 2 MB L2 cache, direct mapped, WB (off-chip) • 256 bit path to main memory, 4 x 64-bit modules • Victim Buffer: to give read priority over write • 4 entry write buffer between D$ & L2$ Instr Data Write Buffer Stream Buffer Victim Buffer

30. Alpha Memory Performance: Miss Rates of SPEC92 I$ miss = 6% D$ miss = 32% L2 miss = 10% 8K 8K 2M I$ miss = 2% D$ miss = 13% L2 miss = 0.6% I$ miss = 1% D$ miss = 21% L2 miss = 0.3%

31. Alpha CPI Components • Instruction stall: branch mispredict (green); • Data cache (blue); Instruction cache (yellow); L2$ (pink) Other: compute + reg conflicts, structural conflicts

32. Pitfall: Predicting Cache Performance from Different Prog. (ISA, compiler, ...) • 4KB Data cache miss rate 8%,12%, or 28%? • 1KB Instr cache miss rate 0%,3%,or 10%? • Alpha vs. MIPS for 8KB Data $:17% vs. 10% • Why 2X Alpha v. MIPS? D$, Tom D$, gcc D$, esp I$, gcc I$, esp I$, Tom

33. Pitfall: Simulating Too Small an Address Trace I$ = 4 KB, B=16B D$ = 4 KB, B=16B L2 = 512 KB, B=128B MP = 12, 200

34. Cache Optimization Summary Technique MR MP HT Complexity Larger Block Size + – 0Higher Associativity + – 1Victim Caches + 2Pseudo-Associative Caches + 2HW Prefetching of Instr/Data + 2Compiler Controlled Prefetching + 3Compiler Reduce Misses + 0 Priority to Read Misses + 1Early Restart & Critical Word 1st + 2Non-Blocking Caches + 3Second Level Caches + 2Better memory system + 3 Small & Simple Caches – + 0Avoiding Address Translation + 2Pipelining Caches + 2 miss rate miss penalty hit time

35. µProc 60%/yr. 1000 CPU “Moore’s Law” 100 Processor-Memory Performance Gap:(grows 50% / year) Performance 10 DRAM 7%/yr. DRAM 1 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 Review: Who Cares About the Memory Hierarchy? • Processor Only Thus Far in Course: • CPU cost/performance, ISA, Pipelined Execution CPU-DRAM Gap • 1980: no cache in µproc; 1995 2-level cache on chip(1989 first Intel µproc with a cache on chip) “Less’ Law?”

36. What happens on a Cache miss? • For in-order pipeline, 2 options: • Freeze pipeline in Mem stage (popular early on: Sparc, R4000)IF ID EX Mem stall stall stall … stall Mem Wr IF ID EX stall stall stall … stall stall Ex Wr • Use Full/Empty bits in registers + MSHR queue • MSHR = “Miss Status/Handler Registers” (Kroft)Each entry in this queue keeps track of status of outstanding memory requests to one complete memory line. • Per cache-line: keep info about memory address. • For each word: register (if any) that is waiting for result. • Used to “merge” multiple requests to one memory line • New load creates MSHR entry and sets destination register to “Empty”. Load is “released” from pipeline. • Attempt to use register before result returns causes instruction to block in decode stage. • Limited “out-of-order” execution with respect to loads. Popular with in-order superscalar architectures. • Out-of-order pipelines already have this functionality built in… (load queues, etc).