Implementation of Interface Synthesis System (3rd Presentation)

1. Implementation of Interface Synthesis System(3rd Presentation) 배 영 환 1999. 11. 9.

2. 연구 진행 상황 • Data Structure 설계 완료 • 프로그램 구현 중 (30%) • Algorithm Revision

3. Embedded System Design Using ARM7/AMBA andDevice Driver Synthesis 배 영 환 1999. 11. 9.

4. Contents • Embedded System Design • AMBA : Advanced Microcontroller Bus Architecture • HW / SW Interface • Synthesis of Device Drivers • Summary

5. Embedded System Design Partitioning Constraints - Area - Performance - Power

6. Decoder ResCntl Arbiter RemPause BusWatch PLL SMI ExtRAM TIC IntMem Ticbox IntCntl APBif Timer Target Architecture : ARM/AMBA ARM7TDMI core XB APB ARM 7TDMI Wrapper HWModule ExtROM ASB

7. Embedded System Design Flow

8. Contents • Embedded System Design • AMBA : Advanced Microcontroller Bus Architecture • HW / SW Interface • Synthesis of Device Drivers • Summary

9. AMBA : Advanced Microcontroller Bus Architecture • ARM Ltd.에서 개발한 Standard On-Chip Bus • high modularity, multi-master, low power • innovative test methodology • 16 - 32 bit bus 구조 • ASB (Advanced System Bus), APB (Advanced Peripheral Bus) 로 구성 • ARM core에 가장 적합한 Bus 구조

10. ASB (Advanced System Bus) • high performance, high bandwidth bus • non-multiplexed address and data buses • support for pipelined bus operation • multiple bus masters : processor, DMA, TIC • multiple bus slave : APB Bridge, SMI, IntRAM • centralized arbiter, decoder • 32bit, 100 MHz clock, 200 Mbytes/sec

11. APB (Advanced Peripheral Bus) • data access is controlled by select and strobe only • low speed, low power peripheral bus : almost zero power consumption when bus is not used • simple unpipelined interface • bridged to ASB through APBbridge • 32bit, 100 MHz clock, 80 Mbytes/sec • timer/counter, interrupt controller, remap and pause controller, UART, external hardwares

12. AMBA 구조

13. ASB Bus Arbitration Scheme

14. Contents • Embedded System Design • AMBA : Advanced Microcontroller Bus Architecture • HW / SW Interface • Synthesis of Device Drivers • Summary

15. HW/SW Interface Dedicated Port based I/O Micro Processor (ARM7TDMI) Hardware Module Memory-mapped I/O Interrupt Handling

16. Memory-mapped & Dedicated port based I/O Address Port Address Port P1 P2 P3 Micro Processor (ARM) R/W Data Port Data Port Dedicated Port Data Bus FIFO P3 P2 P1 F3 F2 F1 ASIC Hardware Memory Map of Micro Processor

17. Memory Map 0xFFFFFFFF Undefined 0xC0000000 0xE0000000 Hardware module ARM Test 0xC0000000 0x8C000000 Advanced Peripheral Bus (APB) Remap and Pause Controller 0x88000000 0x80000000 Timer code 0x84000000 External ROM(16k) 0x70000000 Interrupt Controller 0x80000000 data External RAM(32k) 0x40000000 Reset 후 interrupt vector 복사 0x00000040 Internal RAM(64) 0x00000000 Interrupt 발생시 service routine으로 jump

18. Interrupt Handling Address Bus  Address Port Address Port P1 P2 P3 Micro Processor (ARM) Data Port Data Port IRQ FIQ   Address Port Interrupt Controller Data Bus Data Port  Other interrupt Request

19. handlecoin hwinterface testbench SMI ExtROM ExtRAM IntCntl APBif Interrupt Handling Scenario on AMBA APB nIRQ ARM core Model XB ARM core AMBA Wrapper 01000100 ASB Read, WriteData bus

20. HW/SW Interface Synthesis

21. Contents • Embedded System Design • AMBA : Advanced Microcontroller Bus Architecture • HW / SW Interface • Synthesis of Device Drivers • Summary

22. Software Device Driver

23. Timing Diagram for Device Driver - Software Device Driver may miss some device events Timing diagram of ISA bus read operation

24. Adding Hardware Interface for Detecting Timing Critical Event Micro Processor HW Interface Device

25. FSM for the Hardware Interface

26. Modified Timing Diagram for Device Driver

27. Device Driver Synthesis Algorithm SW Device Driver Partition SW Device Driver HW Device Driver Schedulable Minimumarea Minimum cut lines

28. Device Driver의 HW/SW 분할

29. Device Driver Synthesis Algorithm(E. Walkup, G. Borriello, “Automatic Synthesis of Device Driver for HW/SW Co-design,” Univ. of WA TM, 1994.)(P. Chou, E. Walkup, G. Borriello, “Scheduling for Reactive Real-Time System,” IEEE Micro, July 1994.) • Device driver의 timing diagram으로부터 event graph 구성 • Max-flow Min-Cut 알고리즘을 이용한 초기 분할 (SW Scheduling과 동시에 수행) • Kernighan-Lin 분할 알고리즘을 이용한 반복적인 분할 개선(SW Scheduling과 동시에 수행) • SW part : SW program 생성 • HW part : FSM 생성 -> HW interface

30. Summary • Embedded System Design Flow • Standard On-Chip Bus AMBA • HW/SW Interface • Memory-mapped & Dedicated port based I/O • Interrupt Handling • Device Driver • Device Driver Synthesis Algorithm