Implementation of Interface Synthesis System

1. Implementation of Interface Synthesis System 배 영 환 1999. 9. 28.

2. Contents • The Final Goal and Boundary of Research • Problem Definition • Why Interface Synthesis? • Classification of Interface Synthesis • Previous Works • One AsynchronousInterface Synthesis Algorithm • Limitation of the Algorithm • Conclusions

3. The Final Goal and Boundary of Research • Final Goal • Development of New Interface Synthesis Algorithm • Implementation of Interface Synthesis System • Research Boundary • Asynchronous Interface Synthesis • Input : Timing Diagram • Output : Verilog (or VDHL) Code

4. Problem Definition of Interface Synthesis - Automatically obtaining a customized implementation of the interface between two modules

5. Why Interface Synthesis ? • IP(Intellectual Property) based design • Standard on-chip bus (AMBA, etc) • Separation of interface from core for reusability • Interface design is tedious and error prone task.

6. Classification of Interface Synthesis • Synchronization Scheme • Asynchronous Interface • Synchronous Interface • Communication Media • Point to Point • Bus • Input Description • Timing Diagram • Finite State Machines (Previous Works (I)) • Protocols Written in HDL (Previous Works II))

7. Previous Works (I) • Synthesizing Converters between Finite State Protocols (ICCD’91 - J.Akella) • goal • generation of the state machine of the protocol converter • proposed approach • the FSM part of the protocol converter is obtained from the product of protocol state machine • require a third state machine for inter protocol operation Correct inter-operation state change Product protocol Protocol A Protocol B 0 0 4 1 1 2 3 2 FSM for protocol converter

8. Previous Works (II) • Interfacing Incompatible Protocols using Interface process generation (S.Narayan, DAC, ‘95.) • input : HDL descriptions of the two fixed protocols • output : HDL description of the interface process Protocol : Pa Protocol : Pb Processor Memory (64K x 16b) 8 ADDRp port ADDRp[7:0], ARDYp, DREQp out ; port DATAp[15:0], ARCVp, DRDYp in ; ADDRp <= AddrVar[7:0]; ARDYp <= 1; wait until (ARCVp == 1); ADDRp <= AddrVar[15:8]; DREQp <= 1; wait until (DRDYp == 1); DataVar <= DATAp; port MADDRp[15:0], RDp in ; port MDATAp[15:0] out ; wait until (RDp == 1); MAddrVar <= MADDRp; wait for 100ns; MDATAp <= MemVar(MAddrVar); 8 DATAp ARDYp ARCVp DREQp DRDYp RDp MADDRp 16 MDATAp 16

9. Previous Works (II)(Cont.) • Automatically synthesis interface process using dual operations.

10. Previous Works (II)(Cont.)

11. Previous Works (III) One Asynchronous Interface Synthesis Algorithm (By Michael Kishinevsky, DAC, ‘98, ) Timing Diagram (in Text Form) Signal Transition Graph State Graph State Assignment Output FSM (Verilog, VHDL)

12. Input Timing Diagram

13. Building Signal Transition Graph from Timing Diagram Timing Diagram Signal Transition Graph (Petri Net)

14. Building State Graph Signal Transition Graph (concurrent) State Graph (sequential)

15. State Assignment State Graph

16. Limitation of the Algorithm and Research Directions • Single Transaction • Considering Multiple Transactions • Control Signal Only • Adding Data Transfer Signals • Asynchronous Interface • Extending to Synchronous Interface • No Timing Constraint • Adding Timing Constraints

17. Conclusions • Select one asynchronous interface synthesis algorithm. • Develop improved algorithm until the end of this course. • Implement in C language • Input : Timing Diagram • Output : Verilog (or VHDL) code