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SDD DCS status

SDD DCS status. DCS workshop Oct. 6/7 2005 CERN Vojtech Petracek, CTU Prague. Outline. LV system – production of LVPS modules, certification, tests done/t.b.d. HV system – ISEG system, delivery status FE system – DSC boards, modifed I2C communication, DILBERT, DCU2

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SDD DCS status

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  1. SDD DCS status DCS workshop Oct. 6/7 2005 CERN Vojtech Petracek, CTU Prague

  2. Outline • LV system – production of LVPS modules, certification, tests done/t.b.d. • HV system – ISEG system, delivery status • FE system – DSC boards, modifed I2C communication, DILBERT, DCU2 • PVSS subsystem interface and top-end of SDD DCS

  3. LV system • Last version of LVPS2 module produced on halogen-free PCB, contains interlock inputs • Operation in B field and performance of rack without cooling tested, test in neutron field t.b.d, but the key components were tested with previous prototype • Safety certification in progress • AREMpro starting the mass production NOW, to be ready with 40 modules by the end of year • Q1/06 LVPS modules will be burned-in and checked at CERN, ready to start tests of larger systems

  4. HV system • First ISEG modules arrived to INFN Torino • Module transport to CTU Prague t.b.d • Connecting to PVSS - not much effort expected – coordination with DCS central team needed

  5. FE system • 2 DCS boards available at CTU • Rest of the DCS boards will be purchased Q1/06 • I2C/LVDS communication with SDD DCS chips (DILBERT, DCU2) working • Implementation of DCS boards into the shoe-boxes in progress • Power-up scheme for SDD ladders defined, implementation in progress • DIM server for FE – interface to PVSS - in progress

  6. Communication in FE system DCS board SDD Ladder

  7. PVSS • DIM server for LV under development (now in LV PC, plan for server in crate controler) • DIM for FE – first experiments, future use of “Worms” DIM SW layer on DCS board • PVSS installed and work on Top-end starting • More PVSS training / practise in DCS lab & CERN for students needed

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