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Manufacturing Screens for Assuring FPGA Operating Reliability. MAPLD International Conference September 7, 2005 Birds of a Feather Session J: PLD Failures, Analyses and the Impact on Systems Ronald Lake Aeroflex Colorado Springs www.aeroflex.com/radhardFPGA. Purpose of Investigation.
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Manufacturing Screens for Assuring FPGA Operating Reliability MAPLD International Conference September 7, 2005 Birds of a Feather Session J: PLD Failures, Analyses and the Impact on Systems Ronald Lake Aeroflex Colorado Springs www.aeroflex.com/radhardFPGA MAPLD2005
Purpose of Investigation • Problem / Concern: • How to guarantee ViaLink reliability for assured operation over 15 year mission • Un-programmed ViaLinks remain un-programmed • Programmed ViaLinks remain programmed and stable • Solution • Un-programmed ViaLink stress test • Step stress analysis • Burn-in and operating life test • Post stress ViaLink verification MAPLD2005
ViaLink Stress Test • 100% of un-programmed FPGAs undergo ViaLink stress test • Stress test applied to 100% of ViaLinks • cross • row • column • Standard test for Aeroflex QML manufacturing flow • Three step procedure to check and stress ViaLinks • ViaLink checked at 80% of operating voltage • ViaLink stressed at >140% of maximum operating voltage • ViaLink rechecked at 80% of operating voltage Vpp Fuse Stress Fuse Post-Stress Read Fuse Pre-Stress Read MAPLD2005
ViaLink Step Stress Analysis • Performed for wafer lot manufacturing acceptance • Devices randomly selected from units passing manufacturing stress screen • Step stress applied to all ViaLinks by group • Devices tested to failure • Stress voltage recorded for first failure MAPLD2005
Un-programmed burn-in • Applied to 100% of un-programmed units passing manufacturing stress • Standard step in Aeroflex QML manufacturing flow • 240 hrs of 125°C burn-in at maximum operating conditions (Vcc=2.7V, Vccio=3.6V) • FPGAs dynamically stimulated during burn-in • After burn-in devices tested for quiescent current (Icc, Iccio) and un-programmed electrical test (3 temperature, min/typ/max voltage) • Percent defective allowable (PDA) <5% MAPLD2005
Operating Life Summary • LTOL: 77 test units + 3 control • Randomly selected from multiple wafers • No ViaLink failures at 1000 Hrs stress • <3% change in propagation delay • Minimal change is quiescent and active currents • Units returned to LTOL stress for next 1000 Hr read point • HTOL: 77 test units + 3 control • Randomly selected from multiple wafers • No ViaLink failures at 1000 Hrs stress • <10% change in propagation delay • Minimal change in quiescent and active currents • Units returned to HTOL stress for next 1000 Hr read point MAPLD2005
Post stress ViaLink verify • Performed on random selection of units after completion of stress • Used to examine both programmed and un-programmed ViaLinks • Additional capabilities allow monitoring ViaLink resistance MAPLD2005
Summary • Aeroflex Colorado Springs QML manufacturing flow eliminates weak ViaLink material • Addresses primary failure modes in ViaLink / antifuse based PLDs and FPGAs • Auto-programming of un-programmed ViaLinks • Increasing resistance in programmed ViaLinks • Un-programmed ViaLink stress test lowers post burn-in defective rate <1% units failing three temp electrical test • Life test (HTOL and LTOL) show minimal change in quiescent currents and AC propagation delay paths • Post stress vialink verification shows no gross damage to programmed or un-programmed ViaLinks MAPLD2005
