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Aeroflex RadHard FPGA Reliability Update 10 May 2006

Aeroflex RadHard FPGA Reliability Update 10 May 2006. Gerald Matia Manager, Analytical Services Aeroflex Colorado Springs (719) 594-8137 matia@aeroflex.com. Outline. Qualification Status HTOL / LTOL Stress Status and Results HTOL / LTOL Capacity Static Burn-in Assessment

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Aeroflex RadHard FPGA Reliability Update 10 May 2006

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  1. Aeroflex RadHard FPGA Reliability Update10 May 2006 Gerald Matia Manager, Analytical Services Aeroflex Colorado Springs (719) 594-8137 matia@aeroflex.com

  2. Outline • Qualification Status • HTOL / LTOL Stress Status and Results • HTOL / LTOL Capacity • Static Burn-in Assessment • Reliability Test Vehicles and Test Results • ViaLink Structural and Elemental Analysis Status • Wafer and Package Level ViaLink Monitors • Future Studies • Summary

  3. RadHard Eclipse FPGA Status • QML Q qualification completed August 2005 • Standard Microcircuit Drawing (SMD): 5962R04229 • First QML FPGAs shipped September 2005 • Continuing work on QML V with DSCC and Industry Team • Coming Soon: QML Q+ • Assembled and screened using QML V like flow • For customers requiring a higher quality and reliability level

  4. QML Qualification Compliance Matrix Aeroflex versus Aerospace Team Guidance

  5. Qualification Lot Stress Summary • 3 Wafer lots currently in progress • HTOL • 77 units to 1000 hours (LTPD = 3) • 45 units 1000 to 6000 hours (LTPD = 5) • No ViaLink related failures to date • LTOL • 77 units to 1000 hours (LTPD = 3) • 45 units 1000 to 6000 hours (LTPD = 5) • No ViaLink related failures to date • New wafer lot on order • Delivery in August

  6. RadHard FPGA Low Temperature Operating Life – Timeline (Multiple Lots/6000h)

  7. RadHard FPGA High Temperature Operating Life – Timeline (Multiple Lots/6000h)

  8. HTOL / LTOL Capacity • Implementing Capacity Increase to facilitate faster reliability data collection • Currently 44 Stress boards available • 560 socket positions • 68 additional boards on order • Increases capacity by 544 units • Delivery mid-May 2006 • HTOL Chamber • 1 additional on order • Increases capacity by 26 boards • Delivery July / August • LTOL Chambers • 2 additional on order • Increases capacity by 48 boards • Delivery July / August

  9. Static Burn-in Evaluation • Static burn-in demonstration performed on five programmed qualification lots • This demonstration is to determine if static B/I activated any failure mechanisms not found by dynamic B/I • Programmed HTOL and LTOL lots used (Rel3 pattern) • Lots had completed 120 hours of dynamic B/I during assembly and from between 168 hours and 2000 hours of dynamic life-test stress prior to static B/I • Static stress duration: 24 hours, max. operating voltages • A minimum of 77 units / lot were stressed • A total of 385 devices • No failures found at post static B/I electrical test • 2 additional lots should complete stress and ET by 5/12/06

  10. Operating Life AC Deltas REL 3 FPGA Configuration

  11. REL3 Design: Analysis Issues • Issues Identified with REL3 • Limited number of combinational paths (4) • Shift register chains only measure CLK-Q delays on final stage • Memory test block contains only 128x18 SRAM cell • Hardwired clock lightly loaded • Quadrant clock overloaded • No intermediate taps on delay chains

  12. Test Lessons Learned • Intentionally overloaded clock networks (implemented for design rule validation) corrupt some test results • Race conditions can be manifested by temperature and/or stress • Results in bi-modal distributions on select AC tests • Select functional sub-blocks may be off 1 cycle on data shifts • Next generation test chip will conform to all timing related design rules • Repeatability of test results impacted by multi-temp test flow • Multi-temp flow implemented to minimize device handling on small lots • Iddq measurements very sensitive to small temperature shifts • Increasing device soak times to compensate • Improved thermocouple attachment positioning hardware

  13. Test Lessons Learned • Need built-in oscillator monitoring on the reliability test vehicle • Used on un-programmed devices for speed binning • Include on reliability test vehicle for a “non-ViaLink” AC parameter measurements • Provides ability to distinguish between CMOS vs ViaLink induced shifts • Need Screening enhancements to un-programmed devices: • Increase fault coverage on embedded RAM blocks • Increase IDDQ tests to improve fault detection • Enhance unprogrammed I/O parametric test coverage

  14. REL4 Design: Improvements for Delay Analysis • Enhancement implemented with REL4 • Multiplexing of combinational logic allows for 13 path measurements • Preset function on shift register allows chain of 100 register delays • 11 separate preset register chains measured • 5 additional shift registers used to analyze routing and clocking schemes • Multiple taps on chains allow for measurement of intermediate delays • Memory test evaluates 128x18, 512x4 and 1024x2 SRAM cells • Counters used to evaluate maximum frequency shift • PLL implemented

  15. Rel3: Short Path Delay

  16. Rel3: Medium Path Delay

  17. Rel3: Long Path Delay

  18. Rel3: Core IDDQ Temperature instability induced shift

  19. Structural / Elemental Evaluation • Structural Evaluation (The Aerospace Corp. Lab) • FIB X-sections, SEM / TEM Imaging, EELS (elemental analysis) • Output – 3 dimension model (colorized)

  20. Programmed Via Link TEM Image Aeroflex Programmed ViaLink

  21. Wafer Level ViaLink Test Descriptions • BUVp1 = programming voltage of a single isolated ViaLink • TDVp1 = programming voltage of a single isolated ViaLink • TDVpD = programming voltage of a single ViaLink in the center of an array of an array of fuses • TDVp1K = programming voltage of ViaLinks in an array of 1,000 • TDVp25K = programming voltage of ViaLinks in an array of 25,000

  22. ViaLink Parameter Trends

  23. ViaLink Parameter Trends

  24. ViaLink Parameter Trends

  25. ViaLink Parameter Trends

  26. ViaLink Parameter Trends

  27. Step-Stress Vialink Characterization and Screening (Packaged Units) • Step Stress to failure routine was developed to assess wafer to wafer and lot to lot programming voltage variations • Test program vectors are monitored for the cumulative number failing locations • Testing starts at 3.0 volts and increases in 100mV increments until 100% of vectors fail • The number of failing vectors relate to the number of failing ViaLinks • 3.2 million ViaLinks per device – 100% are stressed • Implemented as an lot and wafer screening tool • Remove any out of family wafers for further study • Resulted in unprogrammed devices initially tested at 3.8 volts to remove all lower end of population • All subsequent tests after the initial test are limited to 3.6 volts to insure no damage (auto-programming) of weak ViaLinks

  28. Step-Stress Vialink Characterization and Screening

  29. Step-Stress Vialink Characterization and Screening

  30. Additional Studies • ViaLink Resistivity Measurements • Attempts to measure scribe line test structures were unsuccessful • The programming infrastructure of the device is not present • Programming was inconsistent • Resitivity measurements were not repeatable • DC stress provided inconsistent results for time to failure • Work in Progress and Plans • Isolate programmed ViaLinks in the array using FIB cuts • Probe metal on each side of ViaLink • Measure resistivity on samples pre and post stress • Sample size TBD • Results available in December

  31. Additional Studies • Read Cycle to Disturb (failure) Testing • In the planning stage – timeline and detailed plan TBD • ViaLinks on a programmed device are only subjected to AC capactive current during operation • Create a test chip with a CMOS inverter driving capacitive loads to characterize the affect on AC delays • Use differing capacitive loads (small, medium, high) • Increase current density to perform accelerated testing • 10 years of operation at 50MHz is equivalent to 1.5 x 1016 cycles

  32. Additional Studies (future) • Accelerated Voltage Stress • Testing for LTOL and HTOL stresses • Core max. operating voltage is 2.75 volts • Stress at up to 3.4 volts • Maintains margin to 3.6 volts maximum test voltage • Allows for chamber noise / spikes • Increases e-field stress for CMOS gate oxide defects for improved screening • Improves packaged device screening for dielectric breakdown, hot carriers and mobile ions • Testing will occur when chamber capacity allows • Activation Energies for Failure Mechanisms • Continue work on validating activation energies published by the wafer foundry and QuickLogic

  33. Summary • Summary • No ViaLink Failures from HTOL or LTOL stress to date • 3 Wafer lots in progress heading toward 6000 hours of stress • Improvements to test program • Better test methodologies • Improved fault coverage • Lessons learned from Rel3 being implemented in new a Reliability Test Vehicle (Rel4) • Improved wafer screening and lot assessment using step stress to failure routine • Capacity Increases for additional reliability data collection • Ability to stress approximately 1000 devices simultaneously in-house • No failures found after static B/I when preceded by dynamic B/I • Future Work • Complete Long Term Reliability Studies (HTOL / LTOL stress) • Complete Structural and Compositional Analysis with Aerospace Corp. • Continue ViaLink resistivity and read cycle studies reliability studies • Complete validation of activation energies • Several others not mentioned in this update

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