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Behavioral Modeling of Data Converters using Verilog-A

Behavioral Modeling of Data Converters using Verilog-A. George Suárez Graduate Student Electrical and Computer Engineering University of Puerto Rico, Mayaguez. Code 564: Microelectronics and Signal Processing Branch NASA Goddard Space Flight Center. Agenda. Introduction

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Behavioral Modeling of Data Converters using Verilog-A

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  1. Behavioral Modeling of Data Converters using Verilog-A George Suárez Graduate Student Electrical and Computer Engineering University of Puerto Rico, Mayaguez Code 564: Microelectronics and Signal Processing Branch NASA Goddard Space Flight Center

  2. Agenda • Introduction • Verilog-A • Objectives • Sample and Hold • Analysis • Jitter Noise • Thermal noise • Model • Simulation results • Generic DAC • Analysis and model • Dynamic element matching • Simulation results

  3. Agenda • Generic ADC • Analysis and model • Simulation results • Flash ADC • Analysis and model • Simulation results • SAR ADC • Analysis and model • Simulation Results • Pipelined ADC • Analysis • 1.5 bit Stage • 1.5 bit ADC

  4. Agenda • 1.5 bit MDAC • Digital Correction • Simulation results • ΣΔ ADC • ΣΔ Modulator • SC integrator analysis • Model • Simulation results • Conclusions • Future Work • Acknowledgements • References

  5. Introduction • Transistor-level modeling and simulation is the most accurate approach for mixed-signal circuits. • It becomes impractical for complex systems due to the long computational time required. Taken form the article: Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A Nitin Mohan, Sirific Wireless www.techonline.com

  6. Introduction • This situation has led circuit designers to consider alternate modeling techniques: • In addition, behavioral modeling can be effectively used in a top-down design approach. www.techonline.com Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A, Nitin Mohan, Sirific Wireless

  7. Phase comparator Loop filter F(s) A=1 A=1 V - V + VCO fo - Vout - Vin + + Introduction System Level (Matlab, C++, SystemC, AHDLs, etc…) Behavioral models Functional Level (SPICE, AHDLs) Transistor Level (SPICE) Layout Top-Down Design Approach

  8. vin vout vref Verilog-A • The Verilog-A is a high-level language developed to describe the structure and behavior of analog systems and their components. • It is an extension to the IEEE 1364 Verilog HDL specification for digital design. • The analog systems are described in Verilog-A in a modular way using hierarchy and different levels of modeling complexity. • The motivation is to invest in a new higher level of abstraction in analog design and its combination with the digital one. `include "constants.vams" `include "disciplines.vams" module COMP (vin, vref, vout); output vout; electrical vout; input vin; electrical vin; input vref; electrical vref; parameter real slope = 100.0; parameter real offset = 0.0 ;

  9. Objectives • Build a set of analog and mixed-signal behavioral models using the Verilog-A AHDL, that allows a high level simulation of ADCs. • Simulate some popular ADCs architectures such as: • Flash ADC • SAR ADC • Pipelined ADC • Simulate other common used mixed-signal circuits such as: • ΣΔModulator • Sample and Hold • Provide a general modeling approach for noise sources and other non-idealities. • Provide performance results for the simulated data converters such as spectrum measures SNR, SNDR, THD etc.

  10. Agenda • Introduction • Verilog-A • Objectives • Sample and Hold • Analysis • Jitter Noise • Thermal noise • Model • Simulation results • Generic DAC • Analysis and model • Dynamic element matching • Simulation results

  11. Cs Φs1 - Φs1 Ron Vin + 1 – exp[-t / (2RonCs)] Vout Cp CL δ Jitter Φs1 x(t+δ) - x(t) ≈ δx(t) Ideal value Vout |H| Time f Sample and Hold Thermal noise Vth ≈ kT/Cs (Opamp noise neglected) εg= 1 - Cs /[ Cs + (Cs + Cp)/A0] • Finite DC gain A0 • Finite GBW • Cp and CL • Defective settling • Linear • Slewing • Partial Slewing

  12. δ ΔV x(t+δ) - x(t) ≈ 2πfinδAcos(2πfinnt) ≈ δx(t) Jitter Noise • Clock jitter is due to the non-uniform sampling of the input signal. • The magnitude of this error is a function of the statistical properties of the jitter and the input signal to the system. • In sampled data systems, when a sinusoidal input is taken, the error introduced by jitter can be modeled by, where δis the sampling uncertainty, this is taken to be a Gaussian random process with standard deviation Δt.

  13. Jitter Noise • It is assumed that is a Gaussian random process with zero mean and standard deviation Δt. Δt -Δt Statistical properties of the jitter Input signal to the system

  14. Thermal Noise • Thermal noise in circuits is because of the random fluctuation of carriers due to thermal energy. • Proportional to the temperature. • It is assumed to be a Gaussian random process with zero mean.

  15. Sample and Hold model Thermal Noise Ideal S&H Filter Vin Vout Defective settling + τ = RonCs Jitter IdealNonideal Vout

  16. Sample and Hold simulation results PSD for sampled signal of 0 dB, fin = 2.5146MHz N = 8192, BW = 25MHz Increase in noise floor due nonidealities

  17. Agenda • Introduction • Verilog-A • Objectives • Sample and Hold • Analysis • Jitter Noise • Thermal noise • Model • Simulation results • Generic DAC • Analysis and model • Dynamic element matching • Simulation results

  18. 2B-1 Vout 2B-2 + B bits … Thermometer decoder 1 unit unit unit unit 0 Generic DAC model including mismatch in units - MSB Dummy 27C 26C 22C 21C C C + Vin Vref Gnd SAR Capacitive DAC, SAH and comparator Generic DAC • Mismatch in DAC units. • INL • Gain error • Offset Mismatch in capacitors! (trimming can reduced it to 0.1% Increase in harmonics content)

  19. g nominal gain εg Gain error vadc va xa wa N bits DAC with mismatch α + q Quantization step INL Integral non-linearity offset εoff Offset error IdealNonideal FS Full scale voltage Offset error = 0.5LSB l1 -FS/(2g) q FS/(2N-1) A (2N-1-1)q Analog output Gain error = 0.5LSB α 1/(1+q εg) offset (l1 εg-εoff)q ε0 (INL)sqrt(27)/(2N-2) wa (1- ε0)xa + xa3 ε0/A2 INL = 0.5LSB ya α(wa + off) Digital input code Generic DAC model

  20. Spread the mismatch error energy across the spectrum generating white or colored noise in the DAC output. Improve the DAC performance by locating the distortion caused by the component mismatch errors in certain frequency bands. Magnitude (dB) Magnitude (dB) Magnitude (dB) Magnitude (dB) f (Hz) f (Hz) f (Hz) DEM • Dynamic Element Matching (DEM) techniques are used to minimize the effect of DAC units mismatch. • DAC DEM techniques can be divided in deterministic and stochastic. • Due to design complexity and non-scalability for modeling purposes it is easier to implement a general stochastic approach using randomization.

  21. 2B-1 DAC 0.1% mismatch unit Vout 2B-2 + unit B bits … … … DEM off Randomize Thermometer decoder 1 unit 0 unit DEM on DEM simulation results By randomizing the DAC units (i.e. using a digital circuitry FSM with a system clock) the effect of the mismatch in the spectrum is reduced by reducing the harmonic distortion. In Verilog-A its rather simple to randomize uniformly the units. Assuming we have a system clock, for each rising edge of the clock signal we randomize the units. if(DEM_enable) begin generate i(1,`DAC_UNITS) begin temp = $dist_uniform(seed, 1, `DAC_UNITS); if(temp - floor(temp) >= 0.5) DEM[i] = ceil(temp); else DEM[i] = floor(temp); end end // Then select units stored in the array DEM[ ] for conversion

  22. Agenda • Generic ADC • Analysis and model • Simulation results • Flash ADC • Analysis and model • Simulation results • SAR ADC • Analysis and model • Simulation Results • Pipelined ADC • Analysis • 1.5 bit Stage • 1.5 bit ADC

  23. g nominal gain εg Gain error vadc va wa xa Ideal ADC N bits α + q Quantization step INL Integral non-linearity offset εoff Offset error IdealNonideal FS Full scale voltage Offset error = 0.5LSB q FS/(2N-1) l1 -FS/(2g) + q/2 A (2N-1-1)q Digital output code Gain error = 0.5LSB α 1/(1+qεg) offset (l1 εg-εoff)q ε0 (INL)sqrt(27)/(2N-2) wa α(wa + off) INL = 0.5LSB ya (1- ε0)xa + xa3 ε0/A2 Analog input Generic ADC model

  24. Generic ADC simulation results PSD plot for 8-bit generic ADC with 0 dB input signal fin of 500.977KHz, Samples = 8192, BW = 2MHz SNDR = 49.82 dB SNR = 49.90 dB THD = -64.668 dB SFDR = 67.461 dB ENOB = 8 bits SNDR = 47.877 dB SNR = 49.455 dB THD = -53.037 dB SFDR = 53.859 dB ENOB = 7.7 bits gain error =0.5LSB, offset error = 0.5LSB and INL = 0.5LSB

  25. Agenda • Generic ADC • Analysis and model • Simulation results • Flash ADC • Analysis and model • Simulation results • SAR ADC • Analysis and model • Simulation Results • Pipelined ADC • Analysis • 1.5 bit Stage • 1.5 bit ADC

  26. +Vref R R - - - - + + + + R N bits … … … … Decoder R R R -Vref Flash ADC • Are made by cascading high-speed comparators. • Are the fastest way to convert an analog signal to a digital signal. • Ideal for applications requiring very large bandwidth. • Typically consume more power than other ADC architectures and are generally limited to 8-bits resolution.

  27. Vdd GBW = gm1/CC I5 = SR*Cc Ibias V - V + Cc I5 CL Flash ADC non-idealities • OPAMP • Finite DC gain • Finite GBW • Input resistance • Output resistance • Bias current • Offset voltage • Slew Rate • Bubbles • It is due the metastability of the comparators. (Future work will try model this effect) Cadence provides a well accepted behavioral model of an non-ideal OPAMP/OTA for the most used AHDLs (Verilog-A, Verilog-AMS and VHDL-AMS)!

  28. Flash ADC simulation results PSD plot for 8-bit Flash ADC with 0 dB input signal fin of 3.01MHz, Samples = 4096, BW = 5MHz IdealNonideal

  29. Agenda • Generic ADC • Analysis and model • Simulation results • Flash ADC • Analysis and model • Simulation results • SAR ADC • Analysis and model • Simulation Results • Pipelined ADC • Analysis • 1.5 bit Stage • 1.5 bit ADC

  30. SAR ADC • Successive-approximation-register (SAR) ADCs) used for medium-to-high-resolution (8 to 16 bits) applications with sample rates under 5 Msps. • Used in portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition. • Provide low power consumption. • An N-bit SAR ADC will require N comparison periods and will not be ready for the next conversion until the current one is complete.

  31. Start CLK EOC Timing control SAH CONV Vin Sample & hold Successive Approximation Register (SAR) + - Anti-aliased signal DAC N bits N bits Register VDAC Vref ¾ Vref CLK ½ Vref Start Vin ¼ Vref SAH Conversion time CONV time bit 3=0 bit 2=1 bit 1=0 bit 0=1 EOC (MSB) (LSB) SAR ADC

  32. SAR 8-bit ADC simulation results Ideal PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz SNDR (dB) 49.823 SNR (dB) 49.949 THD (dB) -65.263 SFDR (dB) 67.353 ENOB 8.0

  33. SAR 8-bit ADC simulation results PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz Increase in harmonics due mismatch in DAC units Ideal SNDR 6.02N+1.76=49.92 dB

  34. SNDR (dB) 43.42 45.95 SNR (dB) 47.43 45.99 THD (dB) -45.61 -66.38 SFDR (dB) 47.74 48.78 ENOB 6.9 7.3 SAR 8-bit ADC simulation results PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of 14.954KHz, Samples = 8192, Bandwidth = 250KHz Increase in harmonics due mismatch in DAC units Ideal SNDR 6.02N+1.76=49.92 dB

  35. Agenda • Generic ADC • Analysis and model • Simulation results • Flash ADC • Analysis and model • Simulation results • SAR ADC • Analysis and model • Simulation Results • Pipelined ADC • Analysis • 1.5 bit Stage • 1.5 bit ADC

  36. Agenda • 1.5 bit MDAC • Digital Correction • Simulation results • ΣΔ ADC • ΣΔ Modulator • SC integrator analysis • Model • Simulation results • Conclusions • Future Work • Acknowledgements • References

  37. Pipelined ADC • Has become the most popular ADC architecture for sampling rates from a few MS/s up to 100MS/s, with resolutions from 8 bits at the faster sample rates up to 16 bits at the lower rates. • Low-power capability. • Allows the use of "digital error correction" and “digital calibration” to greatly reduce the accuracy requirement of the internal flash ADCs and DACs respectively. • Because each sample has to propagate through the entire pipeline before all its associated bits are available there is some data latency.

  38. Pipeline ADC M bits Digital correction N1 bits N2 bits Nk-1 bits Nk bits Registers N1 bits N2 bits Nk-1 bits Nk bits Sample & hold Stage1 Stage2 Stagek-1 Stagek 2N + + k-1 Nk-1 bits - Residue amplifier Nk-1bit ADC Nk-1bit DAC

  39. Pipeline ADC 8-bit (1.5-bit per stage ) dout 8 bits Digital correction 2 bit 2 bit 2 bit 2 bits Φ1 Registers Φ2 2 bit 2 bit 2 bit 2 bits Sample & hold Stage1 Stage2 Stage6 1.5 bit ADC Vin Anti-aliased signal Φ2 Φ1 Φ1 Φ2 Φ1 Φ1 Φ2

  40. 2 MDAC 1.5 bit ADC + + 2 bits - Residue amplifier 1.5 bit ADC 1.5 bit DAC Φ1 Φ2 Vin Φ1 1/4Vref Φ1 - C2 Φ2 Vr Vin + 2 bits - Encoder + C1 Residue + -1/4Vref X - 4:1 MUX 1/2Vref Φ1 0 Φ2 -1/2Vref b1 b0 From ADC 1.5-bit Pipelined Stage Vin Residue

  41. 2 1.5 bit ADC + + 2 bits - Residue amplifier 1.5 bit ADC 1.5 bit DAC 1/4Vref - 10 Digital code Vin + 2 bits Encoder 01 + 00 -1/4Vref - Vin -1/4Vref 1/4Vref Modeled as a Generic ADC with the specified reference levels 1.5-bit ADC

  42. Vin MDAC Residue 2 + + 2 bits - Residue amplifier 1.5 bit ADC 1.5 bit DAC Φ1 Φ2 Vres = Vin(C1+C2)/C1 + Vr Vin Residue Φ1 Vref Φ1 C2 Φ2 Vr 1/2Vref - 0 Vin C1 Residue + -1/2Vref X 4:1 MUX -Vref 1/2Vref Φ1 0 Φ2 -1/4Vref -1/4Vref -1/2Vref b1 b0 From ADC 1.5-bit MDAC

  43. Φ1 Φ2 Vin Φ1 Φ1 C2 Φ2 - Cp |H| C1 + CL X 4:1 MUX 1/2Vref 0 -1/2Vref Φ1 Φ2 From ADC Ideal value Vres Time 1.5-bit MDAC nonidealities Capacitors mismatch Thermal noise Vth ≈ kT/C1 (Opamp noise neglected) • Finite DC gain A0 • Finite GBW, Cp and CL • Defective settling • Linear • Slewing • Partial Slewing εg= C1+(C1+C2+ Cp)/A0

  44. Thermal Noise Vres 1.5bit MDAC Including mismatch + Defective settling VADC 1.5 bit GenericADC 2-bits IdealNonideal 1.5-bit Stage model Vin

  45. Φ2 Φ1 Digital Correction b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] sum sum sum sum sum sum sum + + + + + + + Overflow cout cin cout cin cout cin cout cin cout cin cout cin cout cin a a a a a a b b b b b b a b Register Register Register Register Register Register s1[1] s1[0] Register Register Register Register Register s2[1] s2[0] Register Register Register Register s3[1] s3[0] Register Register Register s4[1] s4[0] Register Register s5[1] s5[0] Register s6[1] s6[0] s7[1] s7[0] sk[1] sk[0] are the bits from stage k

  46. Pipelined 8-bit ADC model (Cadence)

  47. SNDR (dB) 44.922 48.577 SNR (dB) 49.573 49.238 THD (dB) -49.923 -57.082 SFDR (dB) 54.427 61.778 ENOB 7.2 7.8 Pipelined 8-bit ADC simulation results PSD plot for 8-bit Pipelined ADC with 0 dB input signal Input frequency of 1.01MHz, Samples = 8192, Bandwidth = 5MHz

  48. Agenda • 1.5 bit MDAC • Digital Correction • Simulation results • ΣΔ ADC • ΣΔ Modulator • SC integrator analysis • Model • Simulation results • Conclusions • Future Work • Acknowledgements • References

  49. fs xi(t) Anti-alias filter xb(t) x[n] Modulator Digital Filter yo[n] y[n] Analog Digital ΣΔ ADC • Makes use of oversampling and ΣΔ modulation techniques to achieve high resolution. • Used for low bandwidth and high-resolution applications but recently there is great interest for medium to high bandwidth applications. • Due oversampling the requirements of the anti-aliasing filter are reduced.

  50. Digital Filter Lth order contains L integrators Single or Multi-bit depending on the quantizer Signal g1 ∫ N-level Quantizer g2 Magnitude (dB) White Noise Shaped Quantization Noise DAC Frequency (Hz) ΣΔ Modulator (ΣΔM) • ΣΔM is the major analog component of the ADC. • Due to its mixed-signal nature, non-idealities largely affect the performance of the ADC, i.e. the integrator, DAC mismatch. • Quatization noise is shaped outside the band of interest. • Several architectures exists depending on the number of integrators and the quantizer levels.

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