Verilog HDL (Behavioral Modeling)

1. Verilog HDL(Behavioral Modeling) BilalSaqib

2. Behavioral Modeling

3. Structured Procedures

4. A module may contain multiple always statements and multiple initial statements. Each statement starts a separate control flow and starts execution at time 0. In One Module

5. An initial statement executes only once and begins its execution at start of simulation which is at time 0. Syntax : initial [timing_control] procedural_statement Initial statement

6. An always statement executes repeatedly and also begins its execution at start of simulation which is at time 0. Syntax : always [timing_control] procedural_statement Always statement

7. where a procedural_statement is one of : procedural_assignment ( blocking or non_blocking) procedural_continuous _assignment conditional_statement case_statement loop_statement wait_statement disable_statement event_trigger sequential_block parallel_block task_enable (user

8. Procedural Blocks are constructed from the following components. • Procedural Assignment Statements • High-Level Constructs Procedural Blocks

9. Procedural Assignments

10. Execution of Procedural Blocks can be specified in different ways • Simple Delays: #<delay> • Specify delay before and after execution for a number of time steps. • Edge-Sensitive Controls: always @ (<edge><signal>) • Execution occurs only at a signal edge. Optional keywords “posedge” or “negedge” can be used to specify signal edge for execution. Procedural Execution Control

11. NonBlocking v Blocking Assignments

12. NonBlocking v Blocking Assignments

13. Procedural assignment Occurs inside an always statement or an initial statement. Execution is with respect to other statements surrounding it. Drives registers. Uses “ = “ or “ < = “ assignment symbol. No assign keyword Continuous assignment Occurs within a module. Executes concurrently with other statements ; executes whenever there is a exchange of value in an operand on its right-hand side. Drives nets. Uses “ = “ assignment symbol. Uses assign keyword Continuous assignment vs Procedural assignment

14. A block statement provides a mechanism to group two or more statements to act syntactically like a single statement. There are two kinds of blocks in Verilog HDL. These are : • Sequential block ( begin…end ) : Statements are executed sequentially in the given order. • Parallel block ( fork … join ) : Statements in this block execute concurrently. Block statements

15. Statements in a sequential block execute in sequence. Syntax : begin [ : block_id { declarations} ] procedural_statement (s) end Sequential block

16. Statements in a parallel block execute in concurrently. Syntax : fork [ : block_id { declarations} ] procedural_statement (s) join Parallel block

17. Conditional Statements: if else

18. Conditional Statements: case

19. casex and casez

20. Looping Statements: repeat

21. Looping Statements: while

22. Looping Statements: forever

23. Looping Statements: for

24. module FA_Seq (A , B , Cin , Sum, Cout) ; input A , B, Cin ; output Sum, Cout ; reg Sum, Cout ; reg T1, T2, T3 ; always @ ( A or B or Cin ) begin Sum = ( A ^ B ) ^ Cin ; T1 = A & Cin ; T2 = B & Cin ; T3 = A & B; Cout = ( T1 | T2 ) | T3 ; end endmodule Example