Implementation of a noise subtraction algorithm using Verilog HDL

Implementation of a noise subtractionalgorithm using Verilog HDL University of Massachusetts, Amherst Department of Electrical & Computer Engineering, Course 559/659 by Perry Levy, Aseem Pangotra, Stephan Stiglmayr and Thomas Kunkel Team Leader: Prof. Maciej Ciesielski

Noise-subtracting algorithm • Time to frequency transformation • Subtraction of magnitudes • Distortion correction • Frequency to time transformation Algorithm Modules In- / Output FFT Subtraction

Noise-subtracting algorithm Algorithm Modules In- / Output FFT Subtraction

Noise-subtracting algorithm • Serial data • Shifts of 16bits • Storing in 1032 x 32bit memory • Flushing memory to FFT after receiving of 256 pairs of data Algorithm Modules In- / Output FFT Subtraction

Noise-subtracting algorithm State machine Algorithm Flushing memory storing data in memory Reset 256 pairs Modules Buffer emptied In- / Output Emptying buffer Buffering data Mem flushed FFT Subtraction

Noise-subtracting algorithm Block Diagram Address Address generator Data WR RD Algorithm SCLK Valid Flushing Real part Serial shifter LRCLK Output Modules Imaginary 1024 x 32bit RAM Reset Data Data Buffer Done Enable In- / Output Hold FFT 16bit counter Finite state machine Subtraction

Noise-subtracting algorithm • Parallel input and output of variables • 16Bit address, 8Bit data (compatible to microcontroller) • Preset values when resetting Algorithm Modules In- / Output FFT Subtraction

Noise-subtracting algorithm • Implementation of Radix 2 algorithm • Window length 1024 • 16Bit fixed point arithmetics • 2 FFTs at the same time by using real and imaginary signal • Reconstruction afterwards needed Algorithm Modules In- / Output FFT Subtraction

A C + + B D - Wk x Noise-subtracting algorithm • Butterfly structure as fundamental cell Algorithm Modules In- / Output FFT Subtraction

Noise-subtracting algorithm Signal-flow Graph for 8 point FFT f(0) F(0) Algorithm F(1) -1 W0 F(2) -1 Modules W2 F(3) -1 -1 In- / Output W0 F(4) -1 FFT W1 F(5) -1 -1 W0 W2 Subtraction F(6) -1 -1 W2 W3 f(7) F(7) -1 -1

Noise-subtracting algorithm • Sequential implementation • 1Bit shiftdown after each step to prevent overflow • RAM 1024 x 32Bit • Controller (Finite state machine) • Address generator • Coefficient ROM Algorithm Modules In- / Output FFT Subtraction

Noise-subtracting algorithm Block Diagram output_ready input_ready Algorithm bus_select Controller Modules write_en RAM read_en 32 32 Data In In- / Output Data input_mode io_mode fft_mode fft_done io_done Bus ram_addr1 ram_addr2 Butterfly 10 32 32 FFT Processor Data Out Address Generator 10 twiddle Subtraction 10 Coeff. ROM FFT PROCESSOR rom_addr

Noise-subtracting algorithm Delay estimation Algorithm • Input: 512 • FFT processing: 2*512*10 • output: 512 • Sum 11264 clock cycles Modules In- / Output FFT Subtraction

Verilog output 500 400 300 abs(X1) 200 100 0 0 2000 4000 6000 8000 10000 12000 Matlab FFT (32 bit float) 500 400 300 abs(X2) 200 100 0 0 2000 4000 6000 8000 10000 12000 frequency Noise-subtracting algorithm Simulations Algorithm Modules In- / Output FFT Subtraction

Noise-subtracting algorithm Spectra reconstruction Algorithm Re Im Modules Re Im In- / Output Re Im FFT Subtraction

Absolute Error 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 2000 4000 6000 8000 10000 12000 Noise-subtracting algorithm Error compared to 32bit floating point Algorithm Modules In- / Output FFT Subtraction

Time window weighted with hanning function (dumped from FFT memory) 4 x 10 1 0.5 0 -0.5 -1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 4 x 10 1 0.5 0 -0.5 -1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Noise-subtracting algorithm Error compared to 32bit floating point Algorithm Modules In- / Output FFT Subtraction

5 Recontructed Spectra x 10 4 3 Matlab Verilog 2 1 0 0 1000 2000 3000 4000 5000 6000 5 x 10 4 3 2 1 0 0 1000 2000 3000 4000 5000 6000 frequency [Hz] Noise-subtracting algorithm Error compared to 32bit floating point Algorithm Modules In- / Output FFT Subtraction (absolute values plotted)

C.O.R.D.I.C An acroynm for: Coordinate Rotation DIgital Computer

CORDIC was derived by Volder in the 50’s to calculate trigonometric function. CORDIC can also calculate hyperbolic, linear and logarithmic functions. CORDIC processing offers high computational rates  fast enough for demanding DSP tasks. Hardware-efficient algorithm, requires only shifts and adds. CORDIC? WHY USE IT?

THE CORDIC ALGORITHM • Provides an iterative method of performing vector rotations by arbitrary angles using only shifts and adds. • Multiplication by tangent term can be avoided if the rotation angles are restricted to tan()=2^-i. • In digital hardware = simple shift operation. The individual equations can be rewritten rearranged so that: The basic CORDIC-equations for rotation and vectoring mode:

Rotation mode performs Polar to Cartesian transformation by rotating the input vector by a specified angle (given as an argument). Vectoring mode performs Cartesian to Polar transformation by rotating input vector to the x-axis while recording the angle required to make that rotation. Vectoring and Rotation Modes

Word-Parallel Pipelined CORDIC • CORDIC Processor core built around three fundamental modules: • Pre-Processor: manipulates inputs to fit in -1 to +1 rad. so that the algorithm covers entire 2 range. • CORDIC core: performs actual algorithm in parallel using a pipeline of CordicPipe blocks. • Post-Processor: places results in correct quadrant.

RECTANGULAR TO POLAR CONVERSION • Takes two 16-bit signed words as inputs (Xin,Yin) • CORDIC core returns equivalent polar coordinates where Rout is the magnitude and Aout is the angle. • Outputs are in fractional format with the upper 16-bits represent decimal value and lower 4-bits represent fractional value.

POLAR TO RECTANGULAR CONVERSION • Takes 16-bit magnitude from subtraction and stored angle as inputs (Rin, Ain). • CORDIC core returns equivalent rectangular coordinates Xo and Yo. • Core only converges in the range -90 to +90 degrees, must write a pre and post processor so that algorithm covers entire 2 range.

Need to write test bench for rect2polar and polar2rect modules. Need to finish writing pre and post processor for polar2rect module. Need to connect my modules to my partners modules. Need to test and verify that they work well together. FUTURE WORK

Noise-subtracting algorithm Block diagram Beta Algorithm 16 Modules 1 if x>y, else 0 x a Comp In- / Output sel b FFT Sub Subtraction Alpha

Noise-subtracting algorithm • Inputs: two, 16 unsigned bits each • ( A and B) • Multiplication: Alpha and Beta terms • Subtraction: ((original A)-(Alpha*B)) • Comparators: (A > B) out =1, else out =0 • Multiplexer: • (Inputs: Select, A*Beta, subtractor output) • Select = 1, final_out = x • Select = 0, final_out = y Algorithm Modules In- / Output FFT Subtraction

Connect all modules together. Need to write and verify RTL code. Synthesize all code and implement in FPGA. Test FPGA. FUTURE WORK

Implementation of a noise subtraction algorithm using Verilog HDL

Implementation of a noise subtraction algorithm using Verilog HDL

Presentation Transcript

Verilog HDL -Introduction

INTRODUCTION TO VERILOG HDL

Verilog HDL

Lecture 5. Verilog HDL #2

Lecture 5. Verilog HDL #1

Verilog HDL

Introduction to Verilog HDL

Chapter 10 System Specifications Using Verilog HDL

Verilog HDL (Behavioral Modeling)

Lecture 5. Verilog HDL 3

第五章 Verilog HDL

Verilog HDL Basics

Verilog HDL Basics

Verilog HDL (Behavioral Modeling)

Verilog-HDL

Verilog HDL

Chapter 11 VERILOG HDL

Simulation of 16 bit ALU using Verilog hdl

Verilog HDL Tutorial Winter 2003

Verilog HDL -Introduction