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NetFPGA: Reusable Router Architecture for Experimental Research

SIGCOMM PRESTO Workshop 2008. NetFPGA: Reusable Router Architecture for Experimental Research. Jad Naous, Glen Gibb, Sara Bolouki, and Nick McKeown @stanford.edu. 2008. 09. 24 Presented by Jaeryong Hwang. Software & hardware re-use Obstacles of re-using hardware

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NetFPGA: Reusable Router Architecture for Experimental Research

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  1. SIGCOMM PRESTO Workshop 2008 NetFPGA: Reusable Router Architecture for Experimental Research Jad Naous, Glen Gibb, Sara Bolouki, and Nick McKeown @stanford.edu 2008. 09. 24 Presented by Jaeryong Hwang

  2. Software & hardware re-use • Obstacles of re-using hardware • Dependencies of the particular design • No underlying unifying operating system Introduction What is the open-source re-usable hardware? vs Field Programmable Gate Array Need to make FPGA based hardware design more re-usable for network researchers

  3. PC with NetFPGA 1GE FPGA 1GE 1GE Memory 1GE NetFPGA Board What is NetFPGA? NetworkingSoftware running on a standard PC CPU Memory PCI A hardware accelerator built with FPGAdriving Gigabit network links

  4. Who uses the NetFPGA? • Teachers • Students • Researchers • How do they use the NetFPGA? • To run the Router Kit • To build modular reference designs • IPv4 router • 4-port NIC • Ethernet switch, … • Why do they use the NetFPGA? • To measure performance of Internet systems • To prototype new networking systems Who, How, Why

  5. NetFPGA Components Pipeline Interface Details Usage Example: IPv4 Router Outline

  6. NetFPGA Components Verilog EDA Tools (Xilinx, Mentor, etc.) NetFPGA Driver • Design • Simulate • Synthesize • Download 1GE L3 Parse L2 Parse In Q Mgmt 1GE 1GE IP Lookup Out Q Mgmt 1GE Verilog modules interconnected by FIFO interfaces CPU Memory PCI 1GE FPGA 1GE 1GE My Block Memory 1GE

  7. NetFPGA System User Space Linux Kernel CAD Tools Monitor Software Web & VideoServer Browser & Video Client Packet Forwarding Table PCI-e PCI VI VI VI VI NIC NetFPGA RouterHardware GE GE GE GE GE GE (nf2c0 .. 3) (eth1 .. 2)

  8. Example of NetFPGA System NetFPGA NetFPGA NetFPGA Video Client Video Server

  9. Usage Examples • Reference router pipeline • Five stages • Input • Input arbitration • Routing decision and packet modification • Output queuing • Output • Packet-based module interface • Pluggable design IPv4 Router

  10. Usage Examples/IPv4 Router Using “Module Headers”: Inter-Module Communication Ctrl Word (8 bits) Data Word (64 bits) x Module Hdr Contain information such as packet length, input port, output port, … … … y Last Module Hdr 0 Eth Hdr 0 IP Hdr 0 … 0x10 Last word of packet

  11. Usage Examples/IPv4 Router Inter-Module Communication Module i Module i+1 data ctrl wr rdy

  12. Usage Examples/IPv4 Router MAC Rx Queue MAC Rx Queue Eth Hdr: Dst MAC = port 0, Ethertype = IP IP Hdr: IP Dst: 192.168.2.3, TTL: 64, Csum:0x3ab4 Data

  13. Usage Examples/IPv4 Router Rx Queue Rx Queue 0xff Pkt length, input port = 0 0 Eth Hdr: Dst MAC = port 0, Ethertype = IP 0 IP Hdr: IP Dst: 192.168.2.3, TTL: 64, Csum:0x3ab4 0 Data

  14. Usage Examples/IPv4 Router Input Arbiter Rx Q 7 Input Arbiter Pkt … Rx Q 1 Pkt Rx Q 0 Pkt

  15. Usage Examples/IPv4 Router Output Port Lookup Output Port Lookup 0xff Pkt length, input port = 0 0 EthHdr: Dst MAC = 0 Src MAC = x, Ethertype = IP 0 IP Hdr: IP Dst: 192.168.2.3, TTL: 64, Csum:0x3ab4 0 Data

  16. Usage Examples/IPv4 Router Output Port Lookup 5- Add output port header 1- Check input port matches Dst MAC Output Port Lookup 0xff Pkt length, input port = 0 Pkt length, input port = 0 output port = 4 6- Modify MAC Dst and Src addresses 2- Check TTL, checksum 0 EthHdr: Dst MAC = 0 Src MAC = x, Ethertype = IP EthHdr: Dst MAC = nextHopSrc MAC = port 4, Ethertype = IP 3- Lookup next hop IP & output port (LPM) 0 7-Decrement TTL and update checksum IP Hdr: IP Dst: 192.168.2.3, TTL: 64, Csum:0x3ab4 IP Hdr: IP Dst: 192.168.2.3, TTL: 63, Csum:0x3ac2 4- Lookup next hop MAC address (ARP) 0 Data

  17. Usage Examples/IPv4 Router Output Queues Output Queues OQ0 OQ4 Pkt OQ7

  18. Usage Examples/IPv4 Router 0xff Pkt length, input port = 0 output port = 4 0 EthHdr: Dst MAC = nextHopSrc MAC = port 4, Ethertype = IP 0 IP Hdr: IP Dst: 192.168.2.3, TTL: 64, Csum:0x3ab4 IP Hdr: IP Dst: 192.168.2.3, TTL: 63, Csum:0x3ac2 0 Data MAC Tx Queue MAC Tx Queue

  19. Usage Examples/IPv4 Router MAC Tx Queue MAC Tx Queue 0xff Pkt length, input port = 0 output port = 4 0 EthHdr: Dst MAC = nextHopSrc MAC = port 4, Ethertype = IP 0 IP Hdr: IP Dst: 192.168.2.3, TTL: 64, Csum:0x3ab4 IP Hdr: IP Dst: 192.168.2.3, TTL: 63, Csum:0x3ac2 0 Data

  20. Networked FPGAs in Research Managed flow-table switch http://OpenFlowSwitch.org/ Buffer Sizing Reduce buffer size & measure buffer occupancy RCP: Congestion Control New module for parsing and overwriting new packet New software to calculate explicit rates Deep Packet Inspection (FPX) TCP/IP Flow Reconstruction Regular Expression Matching Bloom Filters Packet Monitoring (ICSI) Network Shunt Precise Time Protocol (PTP) Synchronization among Routers

  21. Visit http://NetFPGA.org

  22. NetFPGA Worldwide Tutorial Series SIGCOMM: Seattle, Washington Jiaotong Univ. Beijing, China Eurosys: Glasgow, Scotland Cambridge: England Hot Interconnects & Summer Camp Stanford, California CESNET Brno, Czech Republic SIGMETRICS San Diego, California IISc Bangalore, India NICTA/UNSW: Sydney, Australia

  23. Photos from NetFPGA Tutorials SIGCOMM - Seattle, Washington, USA Beijing, China SIGMETRICS - San Diego, California, USA Bangalore, India EuroSys - Glasgow, Scotland, U.K. http://netfpga.org/pastevents.php and http://netfpga.org/upcomingevents.php

  24. Map of Deployed Hardware (July 2008)

  25. IPv6 Router (in high demand) • TCP Traffic Generator • Valiant Load Balancing • Graphical User Interface (like CLACK) • MAC-in-MAC Encapsulation • Encryption / Decryption modules • RCP Transport Protocol • Packet Filtering ( Firewall, IDS, IDP ) • TCP Offload Engine • DRAM Packet Queues • 8-Port Switch using SATA Bridge • Build our own MAC (from source, rather than core) • Use XML for Register Definitions http://netfpga.org/netfpgawiki/index.php/Module_Wishlist Project Ideas for the NetFPGA

  26. Introduce open-source re-usable NetFPGA Providing a simple interface b/w hardware stages and an easy way to interact with the software Allows developers to mix and match functionality provided by different modules Conclusion

  27. http://NetFPGA.org "NetFPGA: Reusable Router Architecture for Experimental Research“ Jad Naous, Glen Gibb, Sara Bolouki, and Nick McKeown SIGCOMM PRESTO Workshop, Seattle, WA, August 2008 NetFPGA Tutorial slides References

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