Design and System Drivers – Messages

Design and System Drivers – Messages Design technology continues to add low power roadmap techniques Design technology, still unclear how new devices affected it (FinFET) Design technology for 3D continues to spread across chapter Design technology for resilience a fundamental portion of DFM Non-Moore fabrics will require increasingly specialized DT Memory an increasingly important factor for design technology Push to integrate AMS/RF on SoC/SiP despite positive 3D prospects Soaring applications may overhaul driver list: DTV, microservers…

Highlights of 2012-2013 Plans • Design Chapter • Review/next ver of Power-Aware DT roadmap (2012-13) - DONE • Special DT for non-Moore fabrics (SW, AMS/RF, MEMS) (2013) - PENDING • Updates on LCP, DFT, Design Verification; v2 of 3D section (2013) - PENDING • Additional content on (design for) resilience, memory (2012) - PENDING • 2012 (September) – need to have updated tables (extby 1 yr) (2012) - PENDING • System Drivers Chapter • Revisit the AMS/RF “sub-driver” of Consumer SOC driver (2013) - PENDING • Overhaul SOC-CP & CS (TV) models, Embedded Memory (2013) - PENDING • Overhaul Driver list ? Is SOC-CS really a driver? Who is ? (2012) - PENDING • What's the next driver ? Automotive, Medical, Energy. • Update MPU model (&frequency). What about microservers ? (2012) - PENDING • Cross-TWG • CTSG: node timing, additional A-factor updates (2012) - PENDING • How will FinFET, UTBB SOI timing change PPA projections? (2012) - PENDING • Renewal of PIDS roadmaps (compact modelinginteraction) (2012-13) - PENDING • 3D effort with the other TWGs (2012-13) - PENDING

Highlights of 2012-2013 Plans • Design Chapter • Review/next ver of Power-Aware DT roadmap (2012-13) - DONE • Special DT for non-Moore fabrics (SW, AMS/RF, MEMS) (2013) - PENDING • Updates on LCP, DFT, Design Verification; v2 of 3D section (2013) - PENDING • Additional content on (design for) resilience, memory (2012) - PENDING • 2012 (September) – need to have updated tables (extby 1 yr) (2012) - PENDING • System Drivers Chapter • Revisit the AMS/RF “sub-driver” of Consumer SOC driver (2013) - PENDING • Overhaul SOC-CP & CS (TV) models, Embedded Memory (2013) - PENDING • Overhaul Driver list ? Is SOC-CS really a driver? Who is ? (2012) - PENDING • What's the next driver ? Automotive, Medical, Energy. • Update MPU model (&frequency). What about microservers ? (2012) - PENDING • Cross-TWG • CTSG: node timing, additional A-factor updates (2012-13) - DONE • How will FinFET, UTBB SOI timing change PPA projections? (2012-13) - DONE • Renewal of PIDS roadmaps (interaction on compact modeling) (2012-13) - DONE • 3D effort with the other TWGs (2012-13) - PENDING

Design Cost Chart

Power Design Technology Roadmap

Power Design Technology Roadmap NEW: approximate computing, dark Silicon, extreme heterogeneity

New Power Design Technology • Approximate computing • Variable-accuracy computing (e.g., flexibly going from 64b to 16b) • 4D computing: reconfiguration on the fly • AVS ? (e.g., part of DVFS). Margin reduction? • Dark Silicon • “normally-off computing” = “extreme power gating” • Extreme heterogeneity • “coprocessor-dominated architectures” (pervasive heterogeneity; energy-efficiency from specialization; HW accelerators) • “10 x 10”, “13 dwarves”, … • Cf. Intel “accelerators for MPU” vs. Tensilica (or, GPUs, xPUs) • NOTES • Not every product can use all the techniques • Asynchronous could be too late • HW Virtualization and Superscalar factors need to be examined

Highlights of 2012-2013 Plans • Design Chapter • Review/next ver of Power-Aware DT roadmap (2012-13) - DONE • Special DT for non-Moore fabrics (SW, AMS/RF, MEMS) (2013) - PENDING • Updates on LCP, DFT, Design Verification; v2 of 3D section (2013) - PENDING • Additional content on (design for) resilience, memory (2012) - PENDING • 2012 (September) – need to have updated tables (extby 1 yr) (2012) - PENDING • System Drivers Chapter • Revisit the AMS/RF “sub-driver” of Consumer SOC driver (2013) - PENDING • Overhaul SOC-CP & CS (TV) models, Embedded Memory (2013) - PENDING • Overhaul Driver list ? Is SOC-CS really a driver? Who is ? (2012) - PENDING • What's the next driver ? Automotive, Medical, Energy. • Update MPU model (&frequency). What about microservers ? (2012) - PENDING • Cross-TWG • CTSG: node timing, additional A-factor updates (2012-13) - DONE • How will FinFET, UTBB SOI timing change PPA projections? (2012-13) - DONE • Renewal of PIDS roadmaps (interaction on compact modeling) (2012-13) - DONE • 3D effort with the other TWGs (2012-13) - PENDING

Memory as a Key Factor in Future DT Chip Array Circuit Bit Cell Gate Device Physical Figure DESN12 Possible Variability Abstraction Levels

Memory as a Key Factor in Future DT Figure DESN8 Variability-Induced Failure Rates for Three Canonical Circuit Types

Highlights of 2012-2013 Plans • Design Chapter • Review/next ver of Power-Aware DT roadmap (2012-13) - DONE • Special DT for non-Moore fabrics (SW, AMS/RF, MEMS) (2013) - PENDING • Updates on LCP, DFT, Design Verification; v2 of 3D section (2013) - PENDING • Additional content on (design for) resilience, memory (2012) - PENDING • 2012 (September) – need to have updated tables (extby 1 yr) (2012) - PENDING • System Drivers Chapter • Revisit the AMS/RF “sub-driver” of Consumer SOC driver (2013) - PENDING • Overhaul SOC-CP & CS (TV) models, Embedded Memory (2013) - PENDING • Overhaul Driver list ? Is SOC-CS really a driver? Who is ? (2012) - PENDING • What's the next driver ? Automotive, Medical, Energy. • Update MPU model (&frequency). What about microservers ? (2012) - PENDING • Cross-TWG • CTSG: node timing, additional A-factor updates (2012) - PENDING • How will FinFET, UTBB SOI timing change PPA projections? (2012) - PENDING • Renewal of PIDS roadmaps (interaction compact modeling) (2012-13) - PENDING • 3D effort with the other TWGs (2012-13) - PENDING

MTM – AMS/RF “Subdriver” Several emphases in DT, DFT: System verification, Hetero systems Plan: paste high-level block model from AMS/RF -- “core model” Hope to obtain model from additional groups, market analysis E.G. WiFi/GPS/cellular/BT/NFC front-end blocks, tuner/demodulator blocks

Generating Mixed-Fabric Drivers … SoC / SiP Drivers (SoC-CP) SoC / SiP Drivers (SoC-CS) Functional blocks (digital) Functional blocks (non-Moore) GAP Primitive models (Digital) Primitive models (Other) Primitive models (AMS/RF) Device models (ERD) Technology models (Interconnect) Technology models (A&P) Device models (PIDS)

What Drivers? • SOC-Consumer Portable (CP) Driver • What will be future driving applications ? • What Geos would drive them moving forward ? US ? • Are phone and tablet similar enough for SOC-CP projection? • SOC-Consumer Stationary (CS) driver • Is it still a driver ? (orginially abstracted from Cell) • Smart TV processor ? • Kinect ? • Is Signal processing on mobile similar to stationary ?

Proposed changes to MPU Model * CP – Cost-Performance; HP – High Performance ** L2$ and L1$ is per core

Updated MPU Model: UnCore Scaling • “Uncore” (increasing portion of MPU) consists of: • Memory controller(s) • Graphics and display controller(s) • I/O and bus interface controller(s)

SoC / MPU Potential Driver Convergence ? • Ongoing product roadmap and More-Than-Moore impact analysis (WIP) • Recent SoC clock and #cores frequency scaling trends • May need to re-examine existing MPU and/or create new driver • Clock frequency growing at 1.5X every 2 years. • Number of cores growing at 2X every 4 years. • Networking-like SoC scaling: off-chip latency, accelerators, L3 cache • Power limitation under 4W per core (HPC example). • Off-chip speed can be as high as 204 Gbits / sec. • “Mobile” Computing SoCs increasingly competing in server space • Beginning to be used in data centers and cloud computing • Extreme core efficiency (active power <4W, sleep power< 0.5W) • Cores and frequency scaling similar to conventional MPUs

Special DT for non-Moore fabrics • SW, AMS/RF, MEMS, 3D / novel packaging ? • Current design technology still insufficient • Design technology will continue to broaden • What design technology is needed beyond current ideas ? • New 3D / TSV design flows • New multi-physics modeling, simulation, analysis tools • Example: thermal / mechanical analysis (base station) • Example: MEMS + electrical analysis (mobile gaming) • Example: sensors + signal processing (industrial, medical) • Example: software + HW simulation (data center network)

Device Model / PIDS interaction • Agreed to only one low power device in the roadmap • Removed LOP device flavor  from 3 to 2 devices • Still questioning how much CD variation can be tolerated • Should Design content change as we move toward 450 mm ? • Should Design care about node definitions ? • (foundry names vs. ITRS)

Design and System Drivers – Messages Design technology continues to add low power roadmap techniques Design technology, still unclear how new devices affected it (FinFET) Design technology for 3D continues to spread across chapter Design technology for resilience a fundamental portion of DFM Non-Moore fabrics will require increasingly specialized DT Memory an increasingly important factor for design technology Push to integrate AMS/RF on SoC/SiP despite positive 3D prospects Soaring applications may overhaul driver list: DTV, microservers…

Design and System Drivers – Messages