X-Architecture Placement Based on Effective Wire Models

1. X-Architecture Placement Based on Effective Wire Models Tung-Chieh Chen, Yi-Lin Chuang, and Yao-Wen Chang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei, Taiwan March 20, 2007

2. Outline • Introduction • Previous works • New wire model – XHPWL • Applications • Min-cut partitioning placement • Analytical placement • Conclusion

3. Wiring Dominates Nanometer Design • As integrated circuit geometries keep shrinking, interconnect delay has become the dominant factor in determining circuit performance. For 90 nm technology, interconnect delay will account for 75% of the overall delay. Source: Cadence Design System

4. L L Manhattan-architecture X-architecture The X-architecture is a new interconnect architecture based on the pervasive use of diagonal routing in chips, and it can shorten interconnect length and thus circuit delay. Solutions • Timing optimization techniques • Wire sizing • Buffer insertion • Gate sizing • New IC technologies • Copper and low-k dielectrics • X-architecture

5. Manufacturing the X Architecture • X-initiative • was created to advance the usage of the X Architecture by ensuring support for the X Architecture throughout the design and manufacturing cycle. • Impacts on EDA tools: • Placement and Routing • Extraction

6. Placement and Routing for X Architecture • Placement • Simulated annealing • Chen et al., “Estimation of wirelength reduction forλ-geometry vs. Manhattan placement and routing” (SLIP-2003) • Over-simplified: all cells are of unit size • Partitioning placement • Ono, Tilak, and Madden, “Bisection based placement for the X architecture” (ASP-DAC-2007) • X-cutlines does not lead to shorter wirelength • Routing • Multilevel routing system • Ho et al., “Multilevel full-chip routing for the X-based architecture”(DAC-2005) • Global routing • Cao et al., “DraXRouter: global routing in X-architecture with dynamic resource assignment”(ASP-DAC-2006)

7. Partitioning Placement • Teig and Ganley, US Patent 6,848,091 • Ono, Talik, and Madden, ASP-DAC-2007 • Study showed X-cutlines cannot reduce the X wirelength (a) Manhattan cutlines (b) X cutlines Shortest X-wirelength

8. Our Contributions • Propose a new X-half-perimeter wirelength (XHPWL) model • Develop effective x-architecture placers • Min-cut partitioning placement • Using generalized net-weighting method • Analytical placement • Smoothing XHPWL by log-sum-exp functions • Achieve shorter X-routing wirelength than the Manhattan HPWL model for both min-cut partitioning placement and analytical placement.

9. Outline • Introduction • Previous works • New wire model – XHPWL • Applications • Min-cut partitioning placement • Analytical placement • Conclusion

10. X Bounding Box Half-Perimeter Wirelength (HPWL) • Half of the bounding box perimeter length • “X bounding box (XBB)” • The minimum region enclosing all net terminals bounded by 0, 45, 90, 135 degree lines Manhattan Bounding Box C C B B D D A A XHPWL = ½ XBB perimeter length

11. (a) Compute the Manhattan Bounding Box (b) Remove the Dotted Line Segments (c) Add the Oblique Line Segments – + Computing X-Half-Perimeter Wirelength (XHPWL)

12. The XHPWL Function Obtain the Resulting X Bounding Box XHPWL(e) We can apply this new model to both min-cut partitioning and analytical placement algorithms.

13. Outline • Introduction • Previous works • New wire model – XHPWL • Applications • Min-cut partitioning placement • Analytical placement • Conclusion

14. c2 c1 Partitioning Placement Problem • Consider a region to be divided into two subregions. • Find the partitioned results with the minimum wirelength • Cells are put at the center of the subregion • Partition recursively to obtain positions for all cells c2 c1 Minimize wirelength (Minimize interconnect Between subregions)

15. Min-Cut Partitioning • Do not change cutlines • Use net-weighting during min-cut to map partitioning objective to the desired wirelength objective • Selvakkumaran and Karypis proposed to use net-weighting • Technical Report, Dept CSE, UMinnesota, 2004 • Chen and Chang proposed a compact form to minimize MHPWL • ICCAD-2005 • Roy and Markov minimizes Manhattan Steiner wirelength • ISPD-2006

16. t1 t1 t1 c2 c1 (a) All cells are at the left subregion. wirelength( {c1, t1} ) = w1. (b) c2 c1 All cells are at the right subregion. wirelength( {c2, t1} ) =w2. (c) c2 c1 Region center Fixed terminal Cells are at the both subregions. wirelength( {c1, c2, t1} ) = w12. Movable cell Generalized Net-Weighting • Consider a net {v1, v2, …, vm, t1, t2, …, tn} • vi: pin in a movable cell • ti: fixed pin • c1 (c2) is the center of the subregion 1 (2) • Find the following three wirelength values • w1 = wirelength( {c1, t1, t2, …, tn} ) • w2 = wirelength( {c2, t1, t2, …, tn} ) • w12 = wirelength( {c1, c2, t1, t2, …, tn} ) wirelength( ) The desired wire function

17. e1 e2 c1 c2 Partitioning Graph and Edge Weights • Create hypergraph G • Two fixed pseudo nodes to present the two subregions • Movable nodes to present movable cells • Introduce 1 or 2 hyperedges for a net • e1: connecting all movable nodes and the fixed pseudo node corresponding to the subregion that results in a smaller wirelength • e2: connecting all movable nodes

18. e1 e2 (d) t1 t1 t1 ncut = 0 c2 c1 (a) e1 e2 All cells are at the left subregion. wirelength( {c1, t1} ) = w1. (b) (e) c2 c1 ncut = weight(e1) = |w2 – w1| = w2 – w1 All cells are at the right subregion. wirelength( {c2, t1} ) =w2. e1 e2 (f) (c) c2 c1 Partition ncut = weight(e1) + weight(e2) = |w2 – w1| + (w12 – max(w1, w2)) = w12 – min(w1, w2) = w12 – w1 Fixed pseudo node Cells are at the both subregions. wirelength( {c1, c2, t1} ) = w12. Movable node Relation between Cut-Size and Wirelength • Theorem: wirelength = min( w1, w2 ) + ncutsize w2 = w1 + (w2 – w1) w12 = w1 + (w12 – w1) w1 = w1 + 0

19. Min-Cut Placement Flow Select a bin to be partitioned Create the partitioning graph Assign net-weights using generalized net-weighting Find a min-cut bisection result Add large sub-partitions into the bin list Non-empty bin list

20. Experiments on Min-Cut Partitioning • Platform: AMD Opteron 2.6GHz • Min-cut partitioning placer:NTUplace1 (ISPD-2005) • Benchmarks: IBM version 2.0 (8 circuits) • Three different models (for calculating w1, w2, w12) • MHPWL (Manhattan-half-perimeter wirelength) • XHPWL (X-half-perimeter wirelength) • XStWL (X Steiner wirelength) • Use total X Steiner wirelength to evaluate the resulting placement

21. Resulting Wirelengths and CPU times • XHPWL: 1% shorter wirelength, 8% CPU penalty • XStWL: 5% shorter wirelength, 22% CPU penalty

22. X Steiner Wirelength Reductions • XHPWL reduces up to about 2% wirelength • XStWL reduces up to about 6% wirelength 0.00

23. Outline • Introduction • Previous works • New wire model – XHPWL • Applications • Min-cut partitioning placement • Analytical placement • Conclusion

24. Analytical Placement • Minimize W(x) + O(x) • Wire forces: dW(x) / dx • Spreading forces: dO(x) / dx W(x) wirelength function O(x) overlap function Wire forcesMinimize wirelengths Spreading forcesMinimize overlaps

25. C B D A Wirelength Forces and the X Bounding Box Wire Forces in Analytical Placement • Pins on the boundary receive forces to reduce the bounding box size. C B D A Wirelength Forces and the Manhattan Bounding Box B has a wire force. C and D change their force directions.

26. XHPWL(e) Smoothing XHPWL • The wire function needs to be smooth enough for analytical placement to facilitate the minimizing process • XHPWL is not smooth

27. Log-Sum-Exp Function • Use the log-sum-exp function to smooth the max-abs function

28. XHPWL-LSE Function • The smoothed version of the XHPWL function:

29. Wire Forces • Forces are given by the gradient of the wire function Vertical Horizontal

30. Analytical Placement Flow Find an initial placement Minimize: αW + β O Find wire forces (dW/dx) and spreading forces (dO/dx) Move cells Cannot further minimizing Update α and β Spreading enough

31. Experiments on Analytical Placement • Platform: AMD Opteron 2.6GHz • Analytical placer:NTUplace3 (ICCAD-2006) • Benchmarks: IBM version 2.0 (8 circuits) • Three different models • MHPWL (Manhattan-half-perimeter wirelength) • XHPWL (X-half-perimeter wirelength) • Use total X Steiner wirelength to evaluate the resulting placement

32. Resulting Wirelengths and CPU times • 3% less X-Steiner wirelength on average • 15% more CPU time on average

33. X Steiner Wirelength Reductions • XHPWL can consistently reduce X-Steiner wirelengths. • Up to about 5% reduction 0.00

34. Outline • Introduction • Previous works • New wire model – XHPWL • Applications • Min-cut partitioning placement • Analytical placement • Conclusion

35. Summary of Wirelength Reductions • Using both X placement and X routing can reduce 11% to 12% wirelength on average

36. Conclusions • The XHPWL model is effective to minimize the X-architecture wirelength • The generalized net-weighting method for min-cut partitioning placement can incorporate different wire models. • The smoothing XHPWL, XHPWL-LSE, is proposed for analytical placement • Using both X placement and X routing can reduce 11% to 12% wirelength on average • With only 8% to 22% CPU time penalty

37. Thank You! Resulting Placement: IBM01