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Logic Gate Delay Modeling -III

Logic Gate Delay Modeling -III. Bishnu Prasad Das Research Scholar CEDT, IISc, Bangalore bpdas@cedt.iisc.ernet.in. OUTLINE. Delay Model History Static Timing Analysis (STA) Corner Models Drawback of Corner Approach Statistical Static Timing Analysis(SSTA) Summary. Delay Model History.

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Logic Gate Delay Modeling -III

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  1. Logic Gate Delay Modeling -III Bishnu Prasad Das Research Scholar CEDT, IISc, Bangalore bpdas@cedt.iisc.ernet.in

  2. OUTLINE • Delay Model History • Static Timing Analysis (STA) • Corner Models • Drawback of Corner Approach • Statistical Static Timing Analysis(SSTA) • Summary

  3. Delay Model History Courtesy : Synopsys

  4. What to do with Delay Models? • Timing analysis of the whole chip Problem: Given a circuit, find the path(s) with the largest delay (critical paths)

  5. Timing Analysis • Solution: run SPICE and report the results of the simulation • Problem: SPICE is computationally expensive to run except for small-size circuits • WANTED:We need a fast method that produces relatively accurate timing results compared to SPICE

  6. Combinational Blocks • Arrival time in Green • Interconnect delay in Red • Gate Delay in Blue • What is the right mathematical object to represent this physical objects ?

  7. Combinational Blocks as DAG • Use a labeled directed acyclic graph G = <V,E> • Vertices represent gates, primary inputs and primary outputs • Edges represent wires • Labels represent delays • Now what do we do with this?

  8. Static timing analysis • Arrival time A(v) for a node v is time when the signal arrives at node v

  9. 1/2 9/10 2/4 7/7 9/11 5/4 1/2 critical path Static timing analysis C17 from ISCAS’85 benchmarks I1 1/2 2/3 O1 I2 2/4 I3 3/5 I4 2/4 O2 1/2 I5 1/2 I6 • All inputs are arrive at time 0 • Assuming all interconnects have 0 delay • Each gate has rise/fall delay • slack = arrival time – required arrival time  paths with negative slacks need to be eliminated!

  10. 21 MUX 21 MUX delay = 5 delay = 5 a 0 0 out delay = 3 delay = 3 1 b 1 STA can lead to false critical paths • STA assumes a signal would propagate from a gate input to its output regardless of the values of other inputs • What is critical path delay according to STA? • Is this path realizable? • No, actual delay is less than estimated by STA

  11. Signal Arrival Times

  12. Simultaneous Arrival Times

  13. Simultaneous Arrival Times

  14. Limitations of STA • False path • Simultaneous Arrival Time • STA is done across all corners (Computationally Expensive)

  15. Corner Models • Four types of Corner models • Fast Corner • Slow Corner • Slow NMOS Fast PMOS • Fast NMOS Slow PMOS • Typical Corner

  16. Design Corners FF Fast FS TT PMOS FS SS Slow Slow Fast NMOS

  17. Corner Table

  18. Applications of Corners • For Power and race condition like hold time use Fast corner • For Delay simulation use Slow corner • The other two corners are used for circuits which require precise sizing for proper functioning. Ex: Memory and pseudo NMOS circuit.

  19. Limitations of Corner Models • Worst case assumption is insignificant • This leads to over design • Hence more power, area and loss of performance • Need more intelligent accounting of variations

  20. Gate Length Variation [Orshansky, et. al, IEEE Trans. On Sem. Manufacturing, Feb 2004]

  21. Environmental Variations: Vdd [Anirudh Devgan, IBM, Mar 05]

  22. Environmental Variations: Temperature [Anirudh Devgan, IBM, Mar 05]

  23. i Ai o Ao Aj j Statistical Static Timing Analysis Ao = max(Ai+ Dio , Aj+ Djo) Delay is no longer Deterministic, it is a random variable

  24. Addition Operation • Addition operation: The sum of two random number is convolutions of their probability functions. Ao = Ai+ Dio Where Ciis the CDF of Ai . Piois the PDF of Dio.

  25. Max Operation • Max Operation: The CDF of the maximum of two independent random variables is simply the product of the CDF of two variables Ao = Max ( Ai , Aj ) • The CDF of node “o” is given by Co(t) = Ci(t) Cj(t)

  26. 3 3 1 2 2 1->0 1->0 1 2 3 4 1 Arrival time Arrival time Probability of Events (a) A probabilistic event (b) A probabilistic event group

  27. Propagating a Single event

  28. Propagating An event group

  29. z ? I1 O1 I2 I3 I4 y O2 I5 I6 pdf pdf pdf delay delay delay Output of SSTA C17 ISCAS Benchmark

  30. Summary • Static Timing Analysis • Limitations of STA • Corner Models • Limitations of Corner Models in Presence of Process Variation • Statistical Static Timing Analysis

  31. References • For SSTA: • J. J. Liou et.al, “Fast Statistical Timing Analysis by Probabilistic Event Propagation”, DAC pp. 661-666, June 2001. • A. Devgan and C. Kashyap, “Block-based Timing Analysis with Uncertainty,” ICCAD, pp. 607-614, Nov. 2003. • H.Chang, V. Zolotov, S. Narayan and C. Visweswariah, “Parameterized Block-Based Statistical Timing analysis with Non-Gaussian Parameters, Nonlinear Delay Functions,” DAC, pp. 71-76, June 2005. • For Corner Model: • N. H. E. Weste and D. Harris, “CMOS VLSI Design, A circuits and Systems Perspective” 3rd edition

  32. References • Go to solvnet site https://solvnet.synopsys.com/amserver/UI/Login and do an account for these materials • CCS Models • Xin Bao, Khusro Sajid, Elisabeth Moseley, “Timing Sign-off using CCS Libraries at Qualcomm”, Snug 2006 San Jose • Peter Chih-Yang Pong, Steve H. Tsai, “An Investigation of CCS”, Snug Taiwan 2006 • CCS Timing Library Characterization Guidelines

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