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Status of the O PER A DAQ

Status of the O PER A DAQ. J.Marteau S.Gardien, C.Girerd, C.Guérin (electronics), T.Descombes (informatics). CONTENTS. Overview of the global DAQ (internal note n° 31, july 2002) The ETRAX version 1 prototype The clock distribution system Global event building

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Status of the O PER A DAQ

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  1. Status of the OPERA DAQ J.Marteau S.Gardien, C.Girerd, C.Guérin (electronics), T.Descombes (informatics) OPERA WEEK FRASCATI, october 30, 2002

  2. CONTENTS • Overview of the global DAQ (internal note n° 31, july 2002) • The ETRAX version 1 prototype • The clock distribution system • Global event building • Status of the BFOOT version 2 prototype OPERA WEEK FRASCATI, october 30, 2002

  3. GENERIC CONTROLLER BOARD Clock unit External clock EPLD (clock decoder) Commands Synchro orders (optional for delay measurement & ajustement) clock trigger Clock shift Reset Readout signal Processor corewith Ethernet Interface FPGA FIFO F/E readout OPERA WEEK FRASCATI, october 30, 2002 Ethernet JTAG Validation input Ethernet controller F/E controller Power unit Digital Power 5V 3.3V Analog Power 0-5V Power supply 0-8V

  4. TT DAQ SCHEME The TT bi-plane is segmented into 16 digital boards (1 / MaPMT) performing : • F/E (2 LAL chips w. 32 channels) configuration & readout (1/3 p.e. threshold, MUXed output) • A/D conversion • clock reception (10 MHz) & fast clock generation (100 MHz) • event timestamping • continuous system calibration (dark current rate & spectrum, natural radioactivity rate & spectrum) • F/E calibration (internal charge injection) • PM + fiber calibration (LED pulser) clock master card bus_n0 bus_n1 switch Ethernet cables OPERA WEEK FRASCATI, october 30, 2002 Digital board

  5. TT DAQ SCHEME Front-End NODE type Cycle value Free run count value Time stamp format Start run received T : trigger event Constant known delay Cycle increment Cycle counter Cycle 0 Cycle 1 Cycle 2 Cycle n Cycle 0 Trigger event Trigger Event In cycle 0 T 0 45 Cycle 0+1+…+n data Cycle 0 data OPERA WEEK FRASCATI, october 30, 2002 clock ETRAX FPGA Zero suppress. +time FIFO F/E readout 32 ADC ch. / ADC DAQ ch. / ADC / time JTAG validation Ethernet controller

  6. RPC DAQ SCHEME (july, 10th ,Padova) The RPC plane is readout by 9 F/E boards : • the readout sequence starts with the FAST OR coming out of one (at least) FEB • the controller board timestamped the 1st trigger & send it to a dedicated validation card (with a majority trigger) • the FEB are readout serially, data are stored into a FIFO & transmitted (possibly discarded if not validated) • monitoring : the single rates are recorded locally in the controller board Clock master board Controller board switch Validation signal 22 9 F/E boards OPERA WEEK FRASCATI, october 30, 2002

  7. RPC DAQ SCHEME (july, 10th, Padova) • Data format : 1st fired strip # (0-561) / # strips in the cluster (1-32) / validation / timestamp 10 + 5 + 1 + 32 = 48 bits / event / FEB • Data rate : 7 kHz / plane  less than 400 kbits/s / controller board << 100 Mbits/s (ETRAX) • Monitoring : singles rates are recorded locally in the ETRAX (see TT) • Slow control interfaced with the global slow control scheme through Ethernet OPERA WEEK FRASCATI, october 30, 2002

  8. switch TDC board RPC PT DAQ SCHEME • A drift tubes station consists of 4 layers with • 192 drift tubes (768 TDC channels) : • common TDC stop : AND of two nearby RPC planes(max. rate 14 kHz) • TDC chips with 8 inputs will be used for the readout. • TDC boards (6 U format) host 12 chips. • 4 TDC boards connected in a special crate ( VME). • PT controller boards (sequencer / clock / ETRAX) consist of special TDC boards hosted in the crate :option : 1 per 4 TDC boards • requires to implement in the FPGA a specific interface able to control 4 serial links for the R/O of four TDC boards (data format & rate, timing t.b.d.) OPERA WEEK FRASCATI, october 30, 2002

  9. PT DAQ SCHEME • Readout sequence sketch : • Both the TDC & controller boards receive the trigger from RPC • the controller board timestamps this trigger and wait for a readout request from the TDC board. • If all data are zero we could decide either to send the timestamp with a specific flag (no data) or do not send anything • If TDC data are available we start the readout and attach the timestamp to the data (~16 bits / channel /event) • Control signals (6 bits / TDC board) :1 bit CLEAR / 3 bits TEST INTERFACE (2 bit PATTERN, 1 bit START) / 1 bit STOP with delay 0-3 ms from the START / 1 bit ZERO SUPPRESSION OPERA WEEK FRASCATI, october 30, 2002

  10. GLOBAL DAQ SCHEME O/E – E/O converter optical emitter/receiver optical splitter GPS control station O/E – E/O converter clock master card switch switch 31 22 bus_n1 bus_n0 trigger board control. board 2 planes AND switch switch OPERA WEEK FRASCATI, october 30, 2002 9 TDC board 8 FEB TT RPC RPC

  11. Overview of the global DAQ (internal note n° 31, july 2002) • The ETRAX version 1 prototype • The clock distribution system • Global event building • Status of the BFOOT version 2 prototype OPERA WEEK FRASCATI, october 30, 2002

  12. ETRAX version 1 PROTOTYPE • The first prototype of Ethernet controller under development includes : • the readout sequencer : FPGA • an external FIFO • the microprocessor with Ethernet I/O : ETRAX MCM (Multi Chip Module) OPERA WEEK FRASCATI, october 30, 2002

  13. TO-DO LIST • Software developments : • FPGA modules programmation (see next transp.) • serial interface with the clock receiver module  • communication protocol between FPGA & ETRAX  : • the FPGA generates an INTERRUPT signal when • the end of a cycle is reached • the FIFO is half full • the ETRAX should then read a register indicating • the number of the cycle the data belong to • the type of data (RUN, CALIBRATION, PEDESTALS) • the number of data to be read • a cycle status flag (cycle ended or incomplete cycle) • the data are converted into C structures (ex. module/channel/ADC/time) • Hardware developments • choice & order of the components  • board design  • routing and mounting  OPERA WEEK FRASCATI, october 30, 2002

  14. FPGA OPERATIONAL MODULES • Bus interface with ETRAX (address decoder, bus controller) • Control registers • Soft Commands (soft configuration of the hardware) • Readout Sequencer (trigger detection, ADC control, FIFO loading) • Timestamp trigger (External & Internal) • Cycle counter + Cycle timestamp • Calibration pulse generation • Trigger source manager (External, Internal, Calibration pulse) • Interrupt management • - FIFO Configuration • - FIFO Status • - DAC controller (4 channels) • Readout Sequencer Configuration • Readout Sequencer Status • - Extern Hold Delay register • - Calibration Pulse configuration • - Destination channel for monochannel R/O • - Delay Cycle Compensation • - Sample number for oscilloscope mode • - Interrupt Status Register • - FIFO Word Number used • - Front-end configuration registers OPERA WEEK FRASCATI, october 30, 2002 - FIFO Partial Reset - FIFO Master Reset - load front-end config registers - front-end reset - clear DAC - clear INTERRUPT - select readout channel

  15. TT digital board In parallel the TT digital board is under development in Lyon withthe final specifications of the end-cap • Mechanical specifications : ~ 10cm×40cm + height < 3cm(limited by the 3 RJ45 connectors & High Voltage module on the board) • Interface with analog board (Bern), meeting @ CERN (Oct., 4th) • summary on the status of the LAL chip (A.Lucotte, K.Borer) • discussion on possible implementations on vers.2 chip: • calibration signal (2 lines / chip : odd & even channels) • « hits » register (giving the pattern of the triggering channels for redundancy checks like pedestals substraction control) • definition of the analog-to-digital board signals (2 connect. 26 pins) : • MUX, HOLD, Trigger, Hit register, Slow control, Threshold, • Test Pulse, HV monitor, GND, Power • choice of the ADC (cost/perf./exp.) OPERA WEEK FRASCATI, october 30, 2002

  16. SCHEDULE • ETRAX mezzanine available in Lyon  end of January 2003 • Tests + Software developments  february • First prototype of analog board (with LAL vers.1c chip, fewchanges in the pin-out)  end of march • Complete R/O chain (analog + digital) end of may OPERA WEEK FRASCATI, october 30, 2002

  17. Overview of the global DAQ (internal note n° 31, july 2002) • The ETRAX version 1 prototype • The clock distribution system • Global event building • Status of the BFOOT version 2 prototype OPERA WEEK FRASCATI, october 30, 2002

  18. Node card i Bus n1 Target Tracker 31 planes Bus n0 GPS Station antenna Master card 0 Optical/Electrical transceiver Tx Rx Master card i Electrical link MLVDS GPS Bidirectionnal Optical fiber Data + clock mixed PCI card TARGET TRACKER CLOCK DISTRIBUTION SYSTEM OPERA WEEK FRASCATI, october 30, 2002

  19. GEN. FEATURES of the CLOCK DIST. SYSTEM • GPS PCI card : • Synchronize the GPS clock • Encodes desired commands in the clock (FPGA) • Records the time information in a DB • Sends the signal to an optical splitter • Bi-directionnality : • Reception of acknowledgement signals • Propagation time delays measurements (update of delay registers) • The signal is converted into electrical format & distributed to the clock master cards • The clock master / receiver cards : • Receives the encoded commands • Deserializes / serializes the commands and the clock (Hotlink transceivers) • Decodes & executes the commands ( EPLD) • Put the signal on M-LVDS buses  • The signals transit via a standard Ethernet cable (6 wires used) & RJ45 connectors OPERA WEEK FRASCATI, october 30, 2002

  20. GPS STATION : PCI CARD ARCHITECTURE GPS signals (pps, irigb, 10MHz) EPC2 EEPROM HOT Link 923 PECL TX Local bus APEX 20KE PLX 9080 Bidirectionnal optical transceiver Optical fiber OPERA WEEK FRASCATI, october 30, 2002 RX Hot Link 933 To the station

  21. Fifo bank fifo delay measured fifo command fifo incr cptr fifo date GPS STATION : APEX 20 KE BLOCK SCHEME 10Mhz, pps, irigb Hot Link 923 control Decod Local bus Local bus OPERA WEEK FRASCATI, october 30, 2002 select Hot Link 933 registers

  22. Rx Tx Bus n0 Data + clock mixed clock deserializer clock data HOT Link 933 Clock From node EPLD EPM7256 data data HOT Link 923 Bus n1 clock SN65MLVD 202D RJ45 data serializer Clock From node MASTER CARD ARCHITECTURE OPERA WEEK FRASCATI, october 30, 2002

  23. clock HOT Link 933 control serializer Data to Bus n0 Data to Bus n1 select data HOT Link 923 Mux Data from Bus n0 deserializer clk from Bus n0 clk Data valid Data from Bus n1 deserializer clk from Bus n1 Data valid MASTER CARD : EPLD BLOCK SCHEME OPERA WEEK FRASCATI, october 30, 2002

  24. Differential signals Clk data Clk from node RJ45 EPLD EPM7128 Node address Commands sent to the FPGA (reset, reboot, increment counter, …) Address requested Address serialized RECEIVER NODE CARD ARCHITECTURE OPERA WEEK FRASCATI, october 30, 2002

  25. RECEIVER NODE CARD : EPLD BLOCK SCHEME data clk data clk connect node serializer deserializer control Commands sent to the FPGA (reset, reboot, incr cptr, …) OPERA WEEK FRASCATI, october 30, 2002 Address node Addr serializer Addr requested by the FPGA Addr serial

  26. SCHEDULE • First version for the master / 8 receiver clock boards : • all the components have been delivered in the lab • master card (routed & mounted)  mid-november 2002 • receiver cards ended  end of december 2002 • tests ended  mid-february 2003 • implementation on TT digital card  may 2003 • GPS PCI board (// work) : • development  end of november 2002 • definition & electrical scheme  end of february 2003 • routing  mid-april 2003 • mounting  may 2003 OPERA WEEK FRASCATI, october 30, 2002

  27. Overview of the global DAQ (internal note n° 31, july 2002) • The ETRAX version 1 prototype • The clock distribution system • Global event building • Status of the BFOOT version 2 prototype OPERA WEEK FRASCATI, october 30, 2002

  28. EVENT BUILDING : SENSOR, DAQ, MANAGER & NAME SERVICE OPERA WEEK FRASCATI, october 30, 2002

  29. SENSOR TASKS OPERA WEEK FRASCATI, october 30, 2002

  30. TT CALIBRATION PROCEDURE (proposal) • We propose to continuously calibrate the detector during the out-of-spills cycles • RPC tracker : continuous record of singles rates (local histos) • TT tracker procedure : • calibration of the 2 nodes of a module simultaneously • send the local histograms to the global DAQ • pedestal run + electronic calibration (a few seconds) • LED pulsing (1 kHz rate, a few seconds) one side after the other (F/E electronics operated in external / internal trigger mode) • calibrate the next module • Each module may be calibrated every 4-5 hours (assuming 30 seconds per module) OPERA WEEK FRASCATI, october 30, 2002

  31. SENSOR TASKS OPERA WEEK FRASCATI, october 30, 2002

  32. DAQ TASKS OPERA WEEK FRASCATI, october 30, 2002

  33. TIME MEASUREMENTS • We simulate the data rate of the TT (the more constraining for the DAQ) by generating random lists of (channel / ADC / time) data assuming a data rate of 50 Hz / channel • We compare the speed of algorithms / processors to sort the data « plane per plane » (a plane containing 16 nodes) and to write plane sequences on HD (sequence : at least 2 events in a coincidence window of 200 ns) : • The lowest required time amounts to 465 ms for 1 second acquisition cycle • We also measure the time needed to get from all the nodes the packets of data. • Setup : 6 Linux PC’s connected on a switch with Gigabit output + 1 workstation (equipped with Gigabit Ethernet card) • Our preliminary measurements extrapolated to the right number of nodes in OPERA TT gives 472 ms to get the dataof 1 second acquisition cycle • The sum of these 2 numbers show that we have to improve the procedure if we want to collect & sort all the data . Tests are underway. OPERA WEEK FRASCATI, october 30, 2002

  34. MANAGER TASKS OPERA WEEK FRASCATI, october 30, 2002

  35. G.U.I. Firewall HTTP JSP Beans Servlet of Coordination Process OPERA WEEK FRASCATI, october 30, 2002 IIOP SQL MANAGER

  36. Overview of the global DAQ (internal note n° 31, july 2002) • The ETRAX version 1 prototype • The clock distribution system • Global event building • Status of the BFOOT version 2 prototype OPERA WEEK FRASCATI, october 30, 2002

  37. GOALS • DAQ system for PMT testing • DAQ system for scintillator module testing@ the assembly factory • F/E electronics : IDEAS VA-TA (VA32hdr11, TA32cg) • Design : • 4 DAC (1 threshold + 3 Biases VA-TA) • ADC 12 bits 10 MHz • 4 NIM outputs (Trigger out) • Ethernet controller : BFOOT, data rate (1 Mbits / sec) through TCP/IP • 1 external trigger input • 1 time reference input • event timestamp : 10 ns resolution (typ), 5 ns (min) • Read/Write : HTTP commands / LabVIEW interface ( definition ?) • The prototype has been delivered in the lab last week for testing(delays due to the components mounting manufactory) OPERA WEEK FRASCATI, october 30, 2002

  38. PICTURE OF THE COMPLETE R/O CHAIN VA-TA board with the 4 chips & the MaPMTsocket • BFOOT mother board : • EEPROM • FPGA • ADC • RJ45 OPERA WEEK FRASCATI, october 30, 2002 BFOOT mezzanine

  39. The same but on the other side… OPERA WEEK FRASCATI, october 30, 2002

  40. The same but connected … • First tests are going on these days (hope the system will be qualified soon) • Requirements : • Specific needs for the user interface ? • Next order (For the TT demonstration wall ? For tests in the labs ?…) • How many in the assembly factory ? When ? • Limited serie (max. 10) OPERA WEEK FRASCATI, october 30, 2002

  41. CONCLUSIONS • Global DAQ scheme under completion (RPC & PT trackers) • ETRAX « mezzanine » 1st prototype in the electric schematics process (complete board in beginning 2003). The FPGA modules are almost fully operationnal & the communication protocol with the ETRAX is defined. • Clock distribution system : first prototype of clock units for February (tests of the EPLD modules & M-LVDS components) • Event building : the simulation benchmark has given itsfirst (encouraging) results. The implementation of acquisition / calibration procedures is under control • BFOOT version 2 : it’s there. Tests are beginning, results soon. OPERA WEEK FRASCATI, october 30, 2002

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