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Varying Memory Size with TPC-C Performance and Resource Effects

Varying Memory Size with TPC-C Performance and Resource Effects. Jay Veazey and Blaine Gaither Hewlett-Packard Jay.Veazey@hp.com Blaine.Gaither@hp.com. Motivation --- why is this interesting?. More memory increases performance How much? Why exactly?

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Varying Memory Size with TPC-C Performance and Resource Effects

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  1. Varying Memory Size with TPC-CPerformance and Resource Effects Jay Veazey and Blaine Gaither Hewlett-Packard Jay.Veazey@hp.com Blaine.Gaither@hp.com CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  2. Motivation --- why is this interesting? • More memory increases performance • How much? • Why exactly? • Reveal and quantify the underlying causes • Focus is R&D tradeoffs • Performance, cost, schedule, power • How much memory to design into a commercial server? • Is memory latency more important than memory size? CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  3. Experimental Design • Vary memory 32-192 GBytes • Measure • Throughput • Resource utilization • CPU, disk I/O, memory BW, CPI, OS context switches • HP Integrity rx6600 • Itanium 2 9050 CPUs (2S/4C) • About 750 disk drives • TPC-C • Resource intensive • Standard, “coin of the realm”…easy to communicate • Unofficial results CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  4. Throughput • Increase of 48% in throughput CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  5. Resource Utilization Disk I/O and CPU utilization • I/O reduction accounts for 20% of the 48% throughput improvement. • Where’s the rest of it? CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  6. CPI and Memory • As memory is added, CPU cycles are used more efficiently • But this is an effect, not a cause---why does CPI fall? CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  7. CPI and Memory Bandwidth • CPI can change for many reasons, most irrelevant here • Memory accesses are relevant • When a load misses cache, the delay counts toward CPI CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  8. Caches Stabilize with Increasing Memory • Units normalized for throughput • accesses (or misses) / sec / CPU / tpmC • L1 accesses imply that the registers also stabilize CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  9. OS Thread Switches and Memory • Reduced thread switches probably cause of register / cache stabilization --- working sets stay around longer CAECW 2008 -- Salt Lake City -- Veazey & Gaither

  10. Summary and Conclusions • Adding memory increases performance significantly • I/O is reduced, as well as I/O instruction pathlength • Context switches are reduced as a result of less I/O • Fewer memory accesses • Lower CPI • More stable caches and registers CAECW 2008 -- Salt Lake City -- Veazey & Gaither

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