WG5-14 crosscut

1. WG5-14 crosscut 7/11(Fri)@JEITA 402

2. Agenda • Input from Litho to Met.(table MET3) for 2008 update. • Requirements from Litho based on Higashikawa-san materials.

3. Agenda of Telecon. (Inputs to Litho) • Ikeno-san reports that the Japanese ITWG will have new members from Panasonic and Sony • Kawamura-san is arranging a crosscut meeting within Japan about double patterning (June 26⇒7/11) • Alain will check with Alan Allen about technology pacing done • Thomas will report next week on precision numbers for spacer double patterning including schematics done • Bart will send updated tables this week including the new technology pacing and the formulas done • Ben/Alain will check if they can send recently presented mask requirements • All: think about inviting more device metrology experts. We will need more input in this field because of: • Dual patterning • 3D metrology requirements for high-K/MG, FinFET, etc. • Collect SEM Uncertainy data (Ben?) • Emperical formulas (13.5%, 15%, 12% of allowed litho variance): Did this change? • Work on specs for Dual Lines processes • Discuss sampling component of thickness variation (spacer LEE carrier) • How to quantify metrology requirements for the two populations • How is "Aspect ratio capability for Trench structures" defined? (BCD / height?)

4. (continued) • Open items (input needed) • Litho TWG: • Overlay requirements for dual patterning: is this still OL/sqrt(2), OL = Overlay single expsosure • Wafer minimum contact hole size (technology pacing is changed, what is the effect on contact?) • Are there new requirements for Dual Patterning? • FEP: • SWA specification for single exposure (SWA specs odd/even for double exposure are 0.5 degrees, we need to compare this to single exposure side wall angle control) • 3D geometries for: high-K, metal gate • Metrology Uncertainty for gate dielectrics

5. Questions to litho TWG • Contact scaling is final? Formulas. • SWA spec single / double patterning • Is SWA the best metric to use? Height & CD seperately controled • CDU requirements double patterning: ½ or 1/sqrt(2) • OL requirements double patterning • In line control (Metrology and Methodology) for asymmetry patterns. What are the requirements? Further explanation

6. Ref. latest ORTC Breakdown of Double Patterning to check 3D shape Coloring By Ben-san

7. Requirements from Litho (Higashikawa-san materials) • In line control (Metrology and Methodology) for asymmetry patterns • 3D characterization (especially 3D shape) • Scatterometry (or OCD or other alternative?) should cover 2D shape for two populations (dual pitch pattern shapes) • Mask metrology is the same and more critical • CDU　½: Double patterning require ½ of single exposure case • OL　½ : OL budget should go down to1/2(10%) to 1/3(7%) for double patterning. At least ½ this year. • 3DSpacer / asymmetry: Exact 2D or 3D shape metrology is necessary Key: 2D (nested pattern: test structure) metrology for two populations with ½ of PT at the same time

8. Double Exposure Double Patterning Spacer double patterning Mask 1 Mask 1 Mask 1 Print Resist Expose Top Hard Mask Top Hard Mask Resist trenches Hardmask trenches Buffer Oxide Buffer Oxide Device layer Device layer and etch Bottom Hard Mask Bottom Hard Mask Substrate Substrate Substrate Substrate Hard mask Top hard mask etch Spacer formation Mask 2 Mask 2 Coat and Expose expose trenches second Oxide deposition resist CMP Spacer removal Etch Oxide removal Hard mask Develop Bottom and device and etch Hard mask etch layer Figure Litho7-7 from ITRS2007

9. Double patterning: Freezing Mask 1 Expose 1 + Develop Substrate Resist Freeze Thermal Crosslink Plasma/Ion Chemical Treatment UV Cure Resist 2 Coat Mask 2 Expose 2 Develop Freezing process: How the status? More promising ? One of candidates for cost merit.

10. w1 S1 w2 S2 δx Etching bias changes dependent on wall angle and space width(S1,S2) ? CD Dual Lines Δx(Overlay W1 to W2) Pink(W2) S1 S2 S1 Red(W1) 水色(S2) w1 w2 w1 w2 3D profile Asymmetric/Periodic Spacer 2*Pitch Blue(W2) S2 S1 S1 S1 S2 Red(S1) w1 Yellow-green(S2) w1 w1 w1 w1 2*Pitch Changes in wall angle of resist pattern come from optical phenomenon, Both end of nested lines have asymmetry profiles. ? Spacer thickness varies depends on CVD controllability (APC) and etch-back controllability (APC), and space width and local pattern density and etc. ?

11. Scatterometry(Target structure to be measured) Film thickness 2 times of ashing effects (dishing) (A) (B) Different mask materials cause different etching bias SW etch back (C) (D) Target structures are (A), (B), (C), (D) OL and CD measurement patterns are different. But Measurement test structures should not affect chip size.

12. Etching（Structures of final mask for substrate） Single exposure Deposition (A) (B) Cured and raw resist Asymmetry etching Etch back (C) Hard Mask and resist mask CMP + Etch off Reverse Scatterometry should covers measurements of pattern widths, wall angles and overlay.

13. Profile & loading effect Loading effects of etching and CVD depend on not only pattern environment but resist pattern shape. So the shape itself is important requirement of metrology. Requirements of shape should cover not only top CD, bottom CD, height and SWA, but 2D(or 3D) stracture.

14. ITRS meeting Achievable overlay was decided to have a path to about 6nm with known technology (no innovation required, so yellow on the table). This decision was made by looking at a simple error budget based on single machine overlay presentations at SPIE. The biggest unknown factor in the error budget is the process term from wafer distortion and alignment mark detection. The exact number will be updated in July, but the proposal to color yellow down to 6nm is the current plan. For the requirements table, flash overlay is 33% of half-pitch which remains not as aggressive as the 20% of HP for DRAM. Now, the logic overlay requirement will remain at 20%, but this will be discussed again in July. For double patterning, the TWG agreed that a new table should be started just for double patterning - it will include both mask and wafer requirements. The spacer requirements proposal from the European group was accepted, but several additional items are also being considered. For litho-etch-litho-etch (LELE) and spacer, the printed pitch is typically 1:3 so a line showing this would indicate clearly the limits of double patterning. For spacer, the sidewall angle of the printed line is important. A simple calculation of using 2% of CD (or 20% of CDU) would require a sidewall angle control of ~0.5deg. （see slide 16) Spacer thickness variation (not red in the current roadmap) should be tightened by 20% to accommodate this part of the error budget. The group agreed that this should be included, but that the 2% assumption and the calculations should be checked. The spacer etch CDU contribution is already calculated in the error budget so it could be added to the table as well.

15. h W θR θL How to estimate spec. of SW angle? WTop Wall angle WBottom Requirements of side wall angle come from CD budget. SWA-induced CD variation = height X SWA variation. Height is 2 to 2.5 times of critical dimension (minimum CD:W) This “2 to 2.5” value are aspect ration of resist pattern and safe number for pattern collapse.

16. ITRS meeting This comes from slide 20 (ref. spie6518YuanshengAMD.pdf attached file) LER=LWR/sqrt(2) LER-induced CD variation is equal to sqrt(5)/3 of the total CD variation PIDS/FEP/IC/Design/Litho joint meeting: NAND flash scaling will keep the half-pitch scaling from the survey, but delays to the floating gate/charge trap (1 year) and 3D structure (5 years) will be included in the update. Overlay for NAND flash will be 33% of half-pitch and LWR 12% of CD (so not the tightest overlay or LWR). The physical gate scaling will go on a new 3.8 year cycle. The resist to etched gate bias must be worked out between litho and FEP. Metrology cross-TWG: The metrology TWG did not consider the requirements for double patterning overlay and film thickness measurement to be of concern. Requirements for 3D dimensional metrology need to be clarified - how accurate does sidewall angle need to be measured (could be very tight for double patterning) and is line-end sidewall angle needed. The litho TWG corrected the metrology table for mask phase measurement in small features (that exists today). Measurement of EUV power is also difficult to quantify. Simulation cross-TWG: Should prediction accuracy of calibrated model be 3% of CD or tighter? Propose tightening to 1% of CD (litho)

17. Double Patterning Update • As agreed in Kamakura, please find attached my proposal for the dual patterning table in the Y2008 ITRS update, to be forwarded to our ITWG colleagues. • As you can see, I added a line for first pass (physical) CD uniformity and modified the requirements for masking layer(s) form "deposited" to "final" (i.e. just before final etching step). I revised these lines with my colleagues of FEP group, whom I thank a lot for the discussion. • I also updated the values with FLASH-related HP. • Coming to the newly-completed lines, I everywhere supposed that • sigma^2 = sigma^2(CD1_fin) + sigma^2(spacers) + 2*sigma^2(etch), • where sigma^2(etch) was selected like in "dual space approach" in this same table (and two etching steps are required after the first pass has been completed). • Some rational behind the choices I made to separate the contributions due to first pass CD uniformity and spacer process control: I had first investigated the possibility to set sigma(CD1_fin) = sigma(MPU physical gate @ HP) or sigma(CD1_fin) = sigma(MPU physical gate @ gen N-2), where the former choice was intended to set this value to the CD control for a physical gate as wide as the considered HP and the latter to that for a gate physical dimension of two generations before that considered. Both criteria failed, in the sense that zero (or negative) budget remained for the spacer control. • The applied criterium was therefore to set spacer control to a "realistic" value for any node and compute the CD bugdet for pass 1: resulting values for this parameter are not so bad.... • In evaluating uniformity and deviation contribution for spacer process control I assumed that sigma(unif) = 2*dev ? (This is just an idea and more discussion is needed) From Mauro Vasconi (European Litho TWG) This is just an example. Requirements (CD budget) has to be determined for each case of spacer-double patterning. Spacer double patterning methods or structures vary among applied processes. Critical patterns are different among applied devices (FLASH, ASIC, DRAM)

18. Double Patterning – 2007 ITRS Mask Requirements Overlay 20% (Spacer) vs. 8% (DP splitting)

19. CD Variation Components (new) sCD : The total CD Variation; sCD|LER : LER induced CD Variation; sCD|non-LER : non-LER induced CD Variation; Courtesy of AMD

20. Questions to litho TWG • Contact scaling is final? Formulas. • SWA spec single / double patterning • Is SWA the best metric to use? Height & CD seperately controled • CDU requirements double patterning: ½ or 1/sqrt(2) • OL requirements double patterning • In line control (Metrology and Methodology) for asymmetry patterns. What are the requirements? Further explanation

21. Litho table (new) Flash hp shrink update  Intel Micron 34 nm MPU Gate L shrink review  PIDS input DRAM 6F2  4.5F2? This affects Litho-requirements and consequently Met-requirements.