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Systematic Design of Current-Steering DAC

Systematic Design of Current-Steering DAC. R91943047 陳建良 R91943091 郭漢松. Out Line. Introduction Architecture of Current-Steering DAC Characterization and modeling Mismatch Estimative Performance Analysis Systematic Design Flow Experimentation Resultant.

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Systematic Design of Current-Steering DAC

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  1. Systematic Design of Current-Steering DAC R91943047 陳建良 R91943091 郭漢松

  2. Out Line • Introduction • Architecture of Current-Steering DAC • Characterization and modeling Mismatch • Estimative Performance Analysis • Systematic DesignFlow • Experimentation • Resultant

  3. This project presents a systematic design methodology for digital-to -analog (D/A) converter. • The knowledge of matching behavior be applied to design Current-Steering DAC. It can predict the performance and propose the dimension of transistor.

  4. Out Line • Introduction • Architecture of Current-Steering DAC • Characterization and modeling Mismatch • Estimative Performance Analysis • Systematic DesignFlow • Experimentation • Resultant

  5. The typical Current-steering DAC shows in right Fig. It can work in high-speed without OP amplifier. • The Two types of Current-steering DAC are the Binary Weighted and Thermometer Code respectively.

  6. The two type compare of Current- Steering DAC as shown in the table. • The Segmented type includes the Binary Weighted and Thermometer Code advantages.

  7. Floorplan of the DAC

  8. Out Line • Introduction • Architecture of Current-Steering DAC • Characterization and modeling Mismatch • Estimative Performance Analysis • Systematic DesignFlow • Experimentation • Resultant

  9. The MOS of current source will be operating in the saturation region. • The Variance in the drain current be written as The σp is deviation of P and be supplied from the foundry.

  10. Out Line • Introduction • Architecture of Current-Steering DAC • Characterization and modeling Mismatch • Estimative Performance Analysis • Systematic DesignFlow • Experimentation • Resultant

  11. INL and DNL for Current-Steering • For the n bit DAC

  12. The normal output Z • The INL_yield can define To obtain an accurate estimation of the INL_yield, the Monte Carlo simulation has been up.

  13. To determine the dimension of MOS of current source.

  14. Out Line • Introduction • Architecture of Current-Steering DAC • Characterization and modeling Mismatch • Estimative Performance Analysis • Systematic DesignFlow • Experimentation • Resultant

  15. Out Line • Introduction • Architecture of Current-Steering DAC • Characterization and modeling Mismatch • Estimative Performance Analysis • Systematic DesignFlow • Experimentation • Resultant

  16. To design 10 bit current-steering DAC.

  17. Out Line • Introduction • Architecture of Current-Steering DAC • Characterization and modeling Mismatch • Estimative Performance Analysis • Systematic DesignFlow • Experimentation • Resultant

  18. The value of inaccuracy rate is 8.11%. • The estimative INL and DNL from Monte Carlo (σ=0.1%) • The simulation of INL and DNL from HSPICE DNL INL INL DNL

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