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EE 5900 Advanced Algorithms for Robust VLSI CAD , Spring 2009

EE 5900 Advanced Algorithms for Robust VLSI CAD , Spring 2009. Static Timing Analysis and Gate Sizing. Delay Evaluation. 1. Gate delay 2. Interconnect delay. 1. Problem Description. Given a pair of pins, compute pin-to-pin delay and possibly output waveform. Delay. Interconnect. Cell.

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EE 5900 Advanced Algorithms for Robust VLSI CAD , Spring 2009

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  1. EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Static Timing Analysis and Gate Sizing

  2. Delay Evaluation • 1. Gate delay • 2. Interconnect delay Circuit Delay

  3. 1. Problem Description • Given a pair of pins, compute pin-to-pin delay and possibly output waveform Delay Interconnect Cell Cell … Cell Circuit Delay

  4. Circuit Model • For an inverter … Csink … Csink Circuit Delay

  5. Sink Capacitance • Gate capacitance, input capacitance • Given for standard cells • Can be found using SPICE • Apply an AC voltage and measure current • Average over a range of frequency I Circuit Delay

  6. Capacitance Model RC Rd Rd Ctotal Circuit Delay

  7. Interconnect Delay: Elmore Delay • Elmore is used as the delay on interconnect • Easy to compute Circuit Delay

  8. Example 4 1 1 1 1 1 2 3 1 1 1 1 m1_1= –4, m1_2= –7, m1_3= –8, m1_4= –8 Circuit Delay

  9. Application of Elmore Delay • Good • Closed form expression, easy to compute • Useful in circuit design such as gate sizing and buffering. • Bad • Inaccurate • Not useful for timing verification Circuit Delay

  10. Circuit Delay Evaluation - Two Components • Cell delay + interconnect delay • Cell delay is computed using RC or K-factor • Interconnect delay is computed using Elmore delay Interconnect Cell Cell Circuit Delay

  11. Static timing analysis Fast Consider all paths Pessimism by considering false paths which are never exercised Dynamic timing analysis ( simulation ) Depends on input stimulus vectors Do not report timing on false paths With large number of testing vectors Accurate Slow Static vs. Dynamic Timing Analysis Circuit Delay

  12. Wire and Gate Models

  13. Step by Step • Model combinational circuit using the previous slide • Starting from primary input gates, compute the arrival time (AT) at each gate, i.e., compute gate delay and interconnect delay • In order to compute the AT at a gate, the ATs of all its input gates need to be computed • Repeat the above process until the ATs at all primary output gates are computed Circuit Delay

  14. Example of Static Timing Analysis • Arrival time (AT): input -> output, take max 1 4 5 3 2 Circuit Delay

  15. Timing Optimization Should we size up this gate to improve timing? • Arrival time (AT): input -> output, take max Circuit Delay

  16. Timing Optimization- II • Suppose that we have a gate (with same gate type) doubling its width. We roughly have C=10, R=1. • If we change the gate with this new one, what is the new delay? Does not change Circuit Delay

  17. Timing Optimization- III • Suppose that we have a gate (with same gate type) doubling its width. We roughly have C=8, R=1. • If we change the gate with this new one, what is the new delay? Circuit Delay

  18. Timing Optimization- IV • This optimization is called gate sizing. Change the gate size (width) in optimization. • 1. Given multiple choices (implementations) per gate type, find a gate implementation at each gate such that the circuit timing is minimized. • 2. Given multiple choices per gate type, find a gate implementation at each gate such that the circuit timing satisfies the target and the total gate area/power is minimized Circuit Delay

  19. Problem Definition of Gate Sizing Given a timing (delay) target, use smallest power/area gates to meet the timing target In general, smaller power -> larger timing, smaller timing -> larger power.

  20. Delay due to Gate Sizing • Suppose that unit width gate capacitance is c and unit width gate resistance is r. Given gate size wi, • Gate size wi: R  r/wi, C  cwi • Delay is a function of RC • Delay   RiCj   wi/wj

  21. Wire and Gate Models

  22. Combinatorial Circuit Model • Gate size variables x1, x2, x3 • Delay on each gate depends on x a1 a3 x1 a6 D1 D4 D6 D7 a5 a7 a2 a4 Drivers D2 Loads D9 D10 D3 D5 D8 x3 x2

  23. Path Delay • Express path delay in terms of component delay • A component can be a gate or a wire • Delay D for each component • Arrival time afor some components

  24. Gate Sizing • Power/area minimization under delay constraints: • This can be solved efficiently using gpsolve

  25. Gate Sizing using GPSOLVE Follow the steps in gatesizing.m

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