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e -link IP for FE ASICs

e -link IP for FE ASICs. VFAT3/ GdSP ASIC design meeting 19/07/2011. The GBT System. Embedded Electronics. Control Room. A Single Link for: Readout (DAQ) High speed unidirectional (up-link) Trigger data (up-link) Timing Trigger and Control (TTC)

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e -link IP for FE ASICs

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  1. e-link IP for FE ASICs VFAT3/GdSP ASIC design meeting 19/07/2011

  2. The GBT System Embedded Electronics Control Room • A Single Link for: • Readout (DAQ) • High speed unidirectional (up-link) • Trigger data (up-link) • Timing Trigger and Control (TTC) • Clock reference and synchronous control (down-link) • Trigger decisions and control (down-link) • Low and fixed latency • Experiment control (SC/DCS/ECS) • Modest bandwidth (bidirectional link) Optical Link • Custom ASICs in the detectors: • Radiation Tolerant: Total dose & Single Event Upsets • Commercial components in the control room • FPGAs used to implement multi-way transceivers Kostas.Kloukinas@cern.ch

  3. GBT Front End interconnects GBT FE ASICs three differential pairs e-link Data Trigger e-port e-port Demux e-port GBT link FE e-links Framer SerDes 8 ports @ 320 Mbps 16 ports @ 160 Mbps32 ports @ 80 Mbps mux e-port e-port User Buses and I/O signals for Control & Monitoring GBT-SCA Slow Control e-link 1 port @ 80 Mbps Kostas.Kloukinas@cern.ch

  4. GBT-link Packet Format • Fixed packet length: 120bits • Packet transmission rate: 1/25ns • Data transmission rate: 4.8 Gbps • Fixed bandwidth allocation: • Trigger path: 640 Mbps • Control path: 160 Mbps • 1 internal e-link (for GBT management) • 1 external e-link (for GBT-SCA chip) • Data path: 2.56 Gbps • 8 e-links @ 320 Mbps • 16 e-links @ 160 Mbps • 32 e-links @ 80 Mbps • Data flow: • Symmetrical, Bi-directional data transmission. • Transmission of GBT-packets is continuous. • Data from e-link ports are muxed/demuxed in the GBT-link stream. • GBT data path is unaware of the e-link transfer protocol. Kostas.Kloukinas@cern.ch

  5. e-link & e-port Block Diagram e-port e-link PHY RXDATA RXCLK FE ASIC packet RXDATA packet TXDATA TXDATA Clk 80/160/320 MHz • Electrical chip-to-chip interconnect. • Bi-directional, point-to-point, range up to 2 meter • Bitrate: 80 Mbps up to 320 Mbps • User interface: Serial bitstream with no embedded protocol. • Allows for maximum design flexibility. • e-port available as an IP block for integration in FE ASICs Kostas.Kloukinas@cern.ch

  6. Physical Layer (electrical) • SLVS (Scalable Low Voltage Standard) • JEDEC standard: JESD8-13 • Differential voltage based signaling protocol. • Voltage levels compatible with deep submicron processes. • Typical link length runs of 30cm over PCB at 1Gbps. • Low Power, Low EMI • Application in data links for Flat Panel displays in mobile devices. • Mobile Pixel Link, MPL-2 (National semi.) LVDS SLVS specifications brief 2 mA Differential max Line impedance: 100 Ohm Signal: +- 200 mV Common mode ref voltage: 0.2V 400mV 1.2V SLVS 200mV 0.2V Kostas.Kloukinas@cern.ch

  7. e-port SLVS IO pad • Receiver • Power Supply: 1.2V to 1.5V • Power Dissipation: • 300uW @ 320Mbs • <1uW @ power down • Transmitter • Power Supply: 1.2V to 1.5 V • Power Dissipation: • 3.0mW @ 320Mbs • <10uW @ power down • Engineer • Sandro Bonacini – CERN, Switzerland Electrical Specifications Electrical Specifications Programmable Output Current Kostas.Kloukinas@cern.ch

  8. Scenario 1 for “Brainstorming” Downstream Detector electronics Off detector electronics Trigger Commands RX TX Control Data TX RX Trigger Data Readout Data Trigger Commands & Data: clock synchronous & fixed latency Readout Data: Poissonian arrival times. Variable latency with upper limit. Control Data: Low bandwidth, asynchronous, relaxed timing requirements. • e-link @ 320Mbps = 40MB/sec, bidirectional. • Downstream: • Trigger Commands: 4bits/25ns (20MB/sec) • Control Data: 4bits/25ns (20MB/sec) • Upstream: • Trigger Data: 4bits/25ns (20MB/sec) fixed bandwidth • Readout Data: 4bits/25ns (20MB/sec) dynamically allocated bandwidth • Control Data: Kostas.Kloukinas@cern.ch

  9. Scenario 2 for “Brainstorming” Downstream Detector electronics Off detector electronics Trigger Commands RX TX TX RX Trigger Data Readout Data I2C SCA Trigger Commands & Data: clock synchronous & fixed latency Readout Data: Poissonian arrival times. Variable latency with upper limit. Control Data: GBT-SCA chip serving all FE ASICs on a “module”. • e-link @ 320Mbps = 40MB/sec, bidirectional. • Downstream: • Trigger Commands: 8bits/25ns (40MB/sec) • Upstream: • Trigger Data: 4bits/25ns (20MB/sec) fixed bandwidth • Readout Data: 4bits/25ns (20MB/sec) fixed bandwidth Kostas.Kloukinas@cern.ch

  10. Remarks (for brainstorming) • Link Synchronization Mechanisms • Bit-level synchronization provided by GBT e-link • Byte-level synchronization • Frame-level synchronization • Link Protocol • Training pattern for link initialization. • Fixed length frames having an “LHC orbit” structure • Special inter-frame pattern (beam gaps) to maintain synchronization • Trigger Data & Readout Data bandwidth requirements ??? User-defined link protocol Kostas.Kloukinas@cern.ch

  11. Thank You Kostas.Kloukinas@cern.ch

  12. e-link & e-port for GBT-SCA ASIC e-port e-link FIFO Interface RX FIFO RX control PHY RXCLK SCA Network Controller packet RXDATA ATLANTIC Bus packet TX control TXDATA TX FIFO Clk @ 40/80 MHz • Electrical chip-to-chip interconnect. • Bi-directional, point-to-point. • Packet data oriented transaction protocol based on HDLC standard. • Bitrate: 80 Mbps (up to 320 Mbps). • Interconnect range up to 2 meter. • Low Power and SEU error tolerant. • e-port available as an IP block for integration in FE ASICs Kostas.Kloukinas@cern.ch

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