INFN WP3 CMOS ASICs for 3D

1. INFN WP3 CMOS ASICsfor 3D Valerio Re - INFN WP3 AIDA meeting, CERN, February 16, 2011

2. Access to full CMOS wafers WP3 participants From WP3 description: (AGH-UST, CERN, CEA, CNRS-CPPM, CNRS-LAL, CNRS-IPHC, INFN-Pavia, INFN-Pisa and INFN-Milano; lead: INFN) “Complete wafers are needed for most of the post-processing steps that are necessary for TSV. This excludes the use of the MPW (Multi Project Wafer) runs offered by many wafer foundries which deliver only diced chips. However, CMOS MPW runs with wafer access are already planned by projects outside AIDA with WP3 participants participating. These runs will be made available for AIDA for further 3D processing. Additional cost overhead for the full wafer access can be funded by AIDA.”

3. Deliverables, milestones and dates D3.2 : Availability of wafers of ASIC electronics June 30th, 2012 Wafers with ASIC readout chips suited for 3D interconnection will be available, either from dedicated MPW runs or from other projects. MS18:Availability of wafers with ASIC electronics for 3D interconnection  June 30th, 2012 Layout of ASICs in MPW MS20: Qualification of ASIC and sensors for 3D interconnection February 28th, 2013 Laboratory tests

4. ASIC technologyselection • Possible Manufacturers: IBM (via CERN), IBM(via MOSIS), Chartered (via Equipic), Tezzaron/Chartered 3D (via CMP/CMC/MOSIS), UMC, AMS (via EUROPRACTICE), others? • Selection criteria: technology (CMOS 130nm, 90nm…, SiGe) full wafer access 3D MPW offered or supported vias first/middle available in process • The collaborating institutions should present their ability to organize ASICs for 3D integration. This should include design, engineering run organization (only partially paid by AIDA-WP3) and tests. Which selection criteria are fulfilled? Costs? How to procure full wafers? CMOS design rules for compatibility with TSVs and 3D interconnections?

5. Deadlines • The availability of CMOS wafers could be a critical issue. An engineering run is expensive and has to be planned in advance. • We should define CMOS design rules that are compatible with various TSVs and interconnection processes • We should find out if we can convey the effort of WP3 institutions to an engineering run which could be only partially paid by AIDA money. A decision has to be taken relatively soon. • We’ll need to find out which pixel readout chip and/or CMOS sensors and/or digital chip (developed by another project) could be used for AIDA purposes. • On the other hand, it would be nice to design a dedicated chip (possibly an adaptation of an existing one) which is optimized for 3D integration • Obviously this requires manpower andmoney from WP3 institutions

6. Thoughts (I) • As an important AIDA goal, we already discussed the option of qualifying a "via last" process; this could meet the requirements of applications where need for the high-density TSVs of Tezz/Chart is not so stringent. • Actually, this could be true for most of our applications, where we might need TSVs only in peripheral regions corresponding to the bonding pad area (there could advantages related to TSVs in the pixel region, e.g. for power distribution). • This could be a goal for WP3: qualifying a set of processes for 2-layer devices in heterogeneous technologies (e.g. CMOSreadout + sensor, analogCMOS + digitalCMOS, CMOSsensor + digitalCMOS), where the two layers are fabricated independently, and TSVs and interconnections are made externally. • In principle TSVs and intercon could be even made by two different companies. Of course this sounds ambitious, but could open an alternative path to Tezz/Chart.

7. Thoughts (II) • We should select a TSV technology that could be used in a deep submicron CMOS chip, independently of the foundry. • We should consider the opportunity of coordinating the engineering run with the IP blocks task. • WP3 institutions should come forward with proposals for CMOS chips to be developed and/or used in the AIDA framework.