EET 4250

1. EET 4250 Ch. 2: Jump Addressing & Ch. 4: The Processor Acknowledgements: Some slides and lecture notes for this course adapted from Prof. Mary Jane Irwin @ Penn State, Morgan Kaufmann supplemental material for the course text.

2. 32-bit Constants • Most constants are small • 16-bit immediate is sufficient • For the occasional 32-bit constant luirt, constant • Copies 16-bit constant to left 16 bits of rt • Clears right 16 bits of rt to 0 §2.10 MIPS Addressing for 32-Bit Immediates and Addresses lhi $s0, 61 0000 0000 0111 1101 0000 0000 0000 0000 ori $s0, $s0, 2304 0000 0000 0111 1101 0000 1001 0000 0000 EET 4250: Microcomputer Architecture

3. op rs rt constant or address 6 bits 5 bits 5 bits 16 bits Branch Addressing • Branch instructions specify • Opcode, two registers, target address • Most branch targets are near branch • Forward or backward • PC-relative addressing • Target address = PC + offset × 4 • PC already incremented by 4 by this time EET 4250: Microcomputer Architecture

4. op address 26 bits 6 bits Jump Addressing • Jump (j and jal) targets could be anywhere in text segment • Encode full address in instruction • (Pseudo)Direct jump addressing • Target address = PC31…28 : (address × 4) EET 4250: Microcomputer Architecture

5. Target Addressing Example • Loop code from earlier example • Assume Loop at location 80000 EET 4250: Microcomputer Architecture

6. Branching Far Away • If branch target is too far to encode with 16-bit offset, assembler rewrites the code • Example beq $s0,$s1, L1 ↓ bne $s0,$s1, L2 j L1L2: … EET 4250: Microcomputer Architecture

7. Addressing Mode Summary EET 4250: Microcomputer Architecture

8. Chapter 4 The Processor

9. Introduction §4.1 Introduction • CPU performance factors • Instruction count • Determined by ISA and compiler • CPI and Cycle time • Determined by CPU hardware • We will examine two MIPS implementations • A simplified version • A more realistic pipelined version • Simple subset, shows most aspects • Memory reference: lw, sw • Arithmetic/logical: add, sub, and, or, slt • Control transfer: beq, j EET 4250: Microcomputer Architecture

10. Instruction Execution • PC  instruction memory, fetch instruction • Register numbers register file, read registers • Depending on instruction class • Use ALU to calculate • Arithmetic result • Memory address for load/store • Branch target address • Access data memory for load/store • PC  target address or PC + 4 EET 4250: Microcomputer Architecture

11. CPU Overview EET 4250: Microcomputer Architecture

12. Multiplexers • Can’t just join wires together • Use multiplexers EET 4250: Microcomputer Architecture

13. Control EET 4250: Microcomputer Architecture

14. Logic Design Basics §4.2 Logic Design Conventions • Information encoded in binary • Low voltage = 0, High voltage = 1 • One wire per bit • Multi-bit data encoded on multi-wire buses • Combinational element • Operate on data • Output is a function of input • State (sequential) elements • Store information EET 4250: Microcomputer Architecture

15. A Y B A A Mux I0 Y + Y Y I1 ALU B B S F Combinational Elements • Adder • Y = A + B • AND-gate • Y = A & B • Arithmetic/Logic Unit • Y = F(A, B) • Multiplexer • Y = S ? I1 : I0 EET 4250: Microcomputer Architecture

16. D Q Clk Clk D Q Sequential Elements • Register: stores data in a circuit • Uses a clock signal to determine when to update the stored value • Edge-triggered: update when Clk changes from 0 to 1 EET 4250: Microcomputer Architecture

17. Clk D Q Write Write D Clk Q Sequential Elements • Register with write control • Only updates on clock edge when write control input is 1 • Used when stored value is required later EET 4250: Microcomputer Architecture

18. Clocking Methodology • Combinational logic transforms data during clock cycles • Between clock edges • Input from state elements, output to state element • Longest delay determines clock period EET 4250: Microcomputer Architecture