EET 4250

1. EET 4250 Ch. 4: The Processor: Datapath & Control Logic Acknowledgements: Some slides and lecture notes for this course adapted from Prof. Mary Jane Irwin @ Penn State, Morgan Kaufmann supplemental material for the course text.

2. Datapath • First-cut data path does an instruction in one clock cycle • Each datapath element can only do one function at a time • Hence, we need separate instruction and data memories • Use multiplexers where alternate data sources are used for different instructions EET 4250: Microcomputer Architecture

3. R-Type/Load/Store Datapath EET 4250: Microcomputer Architecture

4. Full Datapath EET 4250: Microcomputer Architecture

5. 0 4 35 or 43 rs rs rs rt rt rt rd address address shamt funct 31:26 31:26 31:26 25:21 25:21 25:21 20:16 20:16 20:16 15:11 10:6 15:0 15:0 5:0 The Main Control Unit • Control signals derived from instruction R-type Load/Store Branch opcode always read read, except for load write for R-type and load sign-extend and add EET 4250: Microcomputer Architecture

6. ALU Control • ALU used for • Load/Store: F = add • Branch: F = subtract • R-type: F depends on funct field §4.4 A Simple Implementation Scheme EET 4250: Microcomputer Architecture

7. ALU Control • Assume 2-bit ALUOp derived from opcode • Combinational logic derives ALU control EET 4250: Microcomputer Architecture

8. Datapath With Control EET 4250: Microcomputer Architecture

9. Add 4 Fetch PC = PC+4 Instruction Memory Exec Decode Read Address PC Instruction Fetching Instructions • Fetching instructions involves • reading the instruction from the Instruction Memory • updating the PC value to be the address of the next (sequential) instruction • PC is updated every clock cycle, so it does not need an explicit write control signal just a clock signal • Reading from the Instruction Memory is a combinational activity, so it doesn’t need an explicit read control signal

10. Fetch PC = PC+4 Exec Decode Read Addr 1 Read Data 1 Register File Read Addr 2 Write Addr Read Data 2 Write Data Decoding Instructions • Decoding instructions involves • sending the fetched instruction’s opcode and function field bits to the control unit Control Unit Instruction • reading two values from the Register File • Register File addresses are contained in the instruction

11. 31 25 20 15 10 5 0 R-type: op rs rt rd shamt funct RegWrite ALU control Fetch PC = PC+4 Read Addr 1 Read Data 1 Register File Read Addr 2 overflow Instruction zero Exec Decode ALU Write Addr Read Data 2 Write Data Executing R Format Operations • R format operations (add, sub, slt, and, or) • perform operation (op and funct) on values in rs and rt • store the result back into the Register File (into location rd) • Note that Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File

12. RegWrite ALU control MemWrite overflow zero Read Addr 1 Read Data 1 Address Register File Read Addr 2 Instruction Data Memory Read Data ALU Write Addr Read Data 2 Write Data Write Data MemRead Sign Extend 16 32 Executing Load and Store Operations • Load and store operations involves • compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction • store value (read from the Register File during decode) written to the Data Memory • load value, read from the Data Memory, written to the Register File