Presented by: Nivya Papakannu ECE Department, UMASS Amherst

1. Temperature-Aware Resource Allocation and Binding in High Level SynthesisAuthors: Rajarshi Mukherjee, Seda Ogrenci Memik, and Gokhan Memik Presented by: Nivya Papakannu ECE Department, UMASS Amherst

2. Overview: • Introduction • Temperature-Aware High Level Synthesis • Temperature Model and Assumptions • Resource Allocation and Binding • Experimental Setup & Results • Conclusions

3. Introduction: • Continuous technology scaling following Moore’s Law • Billion transistor IC • Massive computational power • Increase in power density • Increase in temperature • One of the biggest challenges in VLSI design

4. Need for thermal Awareness: • Functional Incorrectness • Carrier mobility decrease • Interconnect resistance increase • Reliability Issues • Electro-migration • Transient and Permanent faults • Thermal Considerations • 10C rise – component failure rate doubles • Non-uniform distribution • “HOTSPOTS” • Leakage Power • Dominant in current technologies • Increasing with future technologies • Exponential dependence on temperature • Higher Temperature  Higher Power

5. Thermal Awareness in HLS: • Can we prevent high temperatures in the first place? • Will power optimization help? • Not always • No individual consideration • Incorporate physical phenomenon in all stages of design flow • Thermal driven floor planning and placement • Thermal Aware High Level Synthesis

6. Thermal Model Analogy between heat transfer and RC circuits Ttot is the temperature contribution due to power dissipation Ptot = Pswitch + Pleakage t = one clock cycle duration Temperature Variation Modeled as exponential transient behavior analogous to electrical time constant RC R : thermal resistance, C: thermal capacitance Leakage Model Leakage has exponential dependence Threshold voltage Vth Temperature T 4th order polynomial to represent Pleakage At 180nm 15% of dynamic power at ambient temperature Doubles every 25C Temperature Model & Leakage Model:

7. Temperature Aware Resource Allocation and Binding: • Scheduled Data Flow Graph • Allocation and Binding • Compatibility graph for each operation type • Operations are vertices • Edges labeled with switched capacitance • Two Modes for optimizing temperature • Temperature constrained resource minimization (TC) • Resource constrained temperature minimization (RC)

8. DFG & Compatibility Graph: R1 R2 For k resources – finds k paths s.t. sum of edge weights is min. 2+ 1+ 1+ 2+ 1 3+ 3+ 2 3 4+ 5+ 4+ 5+ 6+ 4 6+ Data Flow Graph Compatibility Graph

9. Relaxation: • Relaxation • Determine the predecessor or parent of each vertex • Relaxation idea based on Dijkstra’s shortest path algorithm • For each vertex the best parent is determined through which we could reach the vertex by relaxing the vertices based on the constraint criteria. • Temperature Constrained (TC) • Relax vertices that do not violate temperature constraint • Resource Constrained (RC) • Relax vertex with minimum rise in temperature.

10. Temperature Aware Resource Allocation and Binding • Determine the parent of each vertex • Relaxation a b c d e f g swab swbc swcd swde swef swfg

11. Temperature Constrained Resource Allocation and Binding • Determine the parent of each vertex • Relaxation a b c d e f g swab swbc swcd swde swef swfg

12. Temperature Constrained Resource Allocation and Binding • Determine the parent of each vertex • Relaxation a b c d e f g swab swbc swcd swde swef swfg T1 Ta Temperature of R1 a Candidates

13. Temperature Constrained Resource Allocation and Binding • Determine the parent of each vertex • Relaxation (a) (a) (a) (a) (a) (a) a b c d e f g swab swbc swcd swde swef swfg T2 T2 T2 T2 T2 T2 T1 Tab Tac Tag Temperature of R1 a b a c a g Candidates

14. Temperature Constrained Resource Allocation and Binding • Determine the parent of each vertex • Relaxation (a) (a) (b) (b) (a) (b) a b c d e f g swab swbc swcd swde swef swfg T2 T2 T3 T3 T2 T3 T1 X a b c Temperature of R1 Tabe Tac Tabd Candidates a b d a b e a c

15. Temperature Constrained Resource Allocation and Binding • Determine the parent of each vertex • Relaxation (a) (a) (b) (b) (a) (d) a b c d e f g swab swbc swcd swde swef swfg T2 T2 T3 T3 T2 T4 T1 X a b d e Tabe Tac Tabdg Temperature of R1 a b e a c a b d g Candidates

16. Temperature Constrained Resource Allocation and Binding • Determine the parent of each vertex • Relaxation • Select the longest path • Bind to a resource • Shown for temperature constrained binding Resource 1 (a) swbd (b) (b) (a) (d) (a) a b c d e f g swab T2 T2 T2 T3 T3 T4 T1 swdg a b d g R1

17. Resource Constrained Allocation and Binding • Determine the parent of each vertex • Relaxation a b c d e f g swab swbc swcd swde swef swfg T1 Temperature on R1 Ta Candidate a

18. Resource Constrained Allocation and Binding • Determine the parent of each vertex • Relaxation (a) a b c d e f g swab swbc swcd swde swef swfg T1 T2 Tab Temperature on R1 a b Candidate

19. Resource Constrained Allocation and Binding • Determine the parent of each vertex • Relaxation (a) (b) a b c d e f g swab swbc swcd swde swef swfg T1 T2 T3 Tabd Temperature on R1 Candidate a b d

20. Resource Constrained Allocation and Binding • Determine the parent of each vertex • Relaxation (d) (a) (b) a b c d e f g swab swbc swcd swde swef swfg T1 T2 T3 T4 R1 Tabdf Temperature on R1 Candidate a b d f

21. Resource Constrained Allocation and Binding • Determine the parent of each vertex • Relaxation (d) (f) (a) (b) a b c d e f g swab swbc swcd swde swef swfg T1 T2 T3 T4 T5 R1 Tabdfg Temperature on R1 a b d f g Candidate

22. Resource Constrained Allocation and Binding • Determine the parent of each vertex • Relaxation • Returns the longest path • Bind to a resource • Shown for resource constrained binding Resource 1 swfd (a) (b) (d) (f) a b c d e f g swab T1 T2 T3 T4 T5 swbd swfg R1 a b d f g

23. Temperature Aware Resource Allocation and Binding • Determine the parent of each vertex • Relaxation • Select the longest path • Bind to operations a resource • Remove operations from comparability graph • Build new comparability graph • Continue until all operations are bound to a resource c e f swef swce

24. Temperature Aware Resource Allocation and Binding • Successive paths from relaxation represent binding of the operations to a new resource • Post-Processing • Merging/dividing resources Resource 2 Resource 1 swcf (a) swbd (c) (d) (b) a b c d e f g swab swef Ti+1 Ti+1 Ti+1 Ti+1 Ti+1 Ti+1 swdg a b d g R1 c f R2

25. Experimental Flow: Applications in C DFGs of Popular DSP Algorithms DFGs ModelSim Simulation for Switching Activity SUIF Synopsys DC for Capacitance Extraction Scheduler Min-Cost Flow Binding Temperature-Aware Allocation & Binding RC Compare with low power binding TC Binding with optimal switching Min Temperature Binding under RC Min Resource Binding under TC Temperature-Aware Binding

26. Resource Overhead 28% increase in MULs 54% increase in ALUs

27. Experimental Results – Temperature 3.6C 11.9C 11.2C 19.2C Maximum Temperature Reached by ALUs

28. Experimental Results – Temperature 2.7C 7.6C 10.3C 18.9C Maximum Temperature Reached by Multipliers

29. Experimental Results – Leakage Power 9% 2.18 2% Normalized leakage power consumption of the three techniques at 180nm

30. Experimental Results – Total Power 2.38 34% 5% Normalized total power consumption of the three techniques at 180nm

31. Conclusions: • Introduced Resource binding Techniques to create temperature-awareness in HLS • Temperature-aware resource allocation and binding • Effectively minimized the maximum temperature reached by a module • Temperature constrained • Resource constrained • Leakage and total power savings in future technologies • A reliability driven methodology can leverageon this mechanism to prevent or reduce likelihood of hotspots on a chip