Visibility Enhancement for Silicon Debug

2. Visibility Enhancement for Silicon Debug Yu-Chin Hsu, Furshing (Kevin) Tsai, Wells Jong, Ying-Tsai Chang

3. Outline • Motivation • Design for Debug methodology • Challenges in debug using silicon data • Visibility Enhancement techniques • Experimental results • Summary

4. Bottleneck in Prototype-to-Volume Time • Smaller design margins – increasing chance of performance failures • Unmodeled defects – higher tester escapes • More transistors – increasing time to isolate physical defects • Greater device complexity – requiring more time and vectors to validate Concept Silicon Prototype Volume Design Test/Debug 7 to 8 monthsDecreasing 6 to 7 monthsIncreasing! Data Quest (2002, 2004) report

5. Test APP × ? OK? ? ? ? × ? Silicon Testing Issues • Functional design errors not detected pre-silicon due to constraints • Structured tests (ATPG, BIST, etc.) do not replicate real-world conditions, resulting in “over-testing” and “under-testing”, examples: • High power consumption - voltage drops - change in VTH: chip rejected • Crosstalk effects - pattern sensitive – not targeted: chip passed • Defects difficult to model escape detection by testers • System-level testing is the ultimate environment where defects are found

6. On-chip Hardware - Design-for-Debug • Debugging silicon in situ easier when designed with “visibility” into internal nodes • Logic which brings out data from the silicon while in the system is known as “design-for-debug” (DFD) logic • IJTAG – on top of DFT • On chip trace buffer • Most DFD today is proprietary, although DFD commercial offerings are increasing • DFD utilized when failures occur during system validation

7. DFD Scancontrol Real-timeclock &resetcontrol Combinationallogic DFT Design-for-Debug (DFD) on the Chip - Example • DFD is not the same as DFT:Debug logic must function during system-level operation • Many DFD implementations leverage DFT circuitry: • IEEE 1149.1 controller (boundary scan) • Internal scan chains (full scan) • DFD is the access mechanism that provides in-situ scan register visibility

8. Complete System for Silicon Debug • On-chip DFD typically hooks up to a pod and is activated by a separate software-based control program • The pod is a device that makes the electrical characteristics between the DFD port and the PC port compatible • The DFD control program accesses data such as the internal register • The limited data is then processed to maximize visibility into design operation pod APP scandata Visibilityenhancement Debug

9. Challenges in DFD Data Analysis • Limited resource available – only a subset of signals can be probed • Limited visibility – only a subset of signals can be extracted from silicon • Low level of abstraction – unfamiliar design to designer

10. Visibility Enhancement -- Overview • Visibility Planning • Analyze design (RTL, gate) and provide optimal (minimal and sufficient) set of signals to be observed • Provide visibility tradeoff information – “expansion potential” of candidate signals • Data Expansion • Process limited data and expand (regenerate) missing signal information for exploration and debug • On-the-fly operation for optimal performance • Abstraction Correlation • Map gate-level signals and instances back to RTL origin • Translate gate-level signal information (waveform data) to match RTL design for designer-level debug

11. Silicon debug with DFD and Visibility Enhancement Visibility Planning Data Expansion & Abstraction Correlation

12. Visibility Analysis (VA) engine determines which set of signals are essential for data expansion A signal value can be made visible if its parent (preceding gate) is visible Primary inputs are considered visible Visibility Analysis and Planning

13. Data expansion (DE) engine makes limited data useful – more visibility Boolean calculation of unobserved combinational network values Maximize value computation thru use of “Don’t Care” truth table results DE metric: signals-with-values/total-number-of-signals Performance optimized by expanding only the logic under investigation and no simulation-like timing wheel 1 0 0 1 1 1 ? 1 ? 1 1 0 Data expansion 0 0 ? ? 1 ? 1 1 ? 0 1 0 1 0 0 ? ? ? 1 0 ? 0 0 1 0 ? 0 0 1 ? 1 1 ? 1 0 0 1 1 1 1 1 Data Expansion

14. Data Expansion - Requirements • Raw signal data obtained from chip is stream of 0’s and 1’s • Control application must make the data usable for analysis applications • Steps for the control application: • Assign temporal information – relative cycle time must be associated with each scan dump • Map each value to an HDL signal • Output the results in a usable format - VCD (IEEE 1364-2001) or FSDB (Novas)

15. On-the-fly Data Expansion • Large volume of data to be generated if computed in bath mode. HDL Source Gate/RTLSignal Values Debug Dataexpansion Gate Netlist On-demand value request Netlist Register Values Silicon w/DFD FSDB

16. Debug at Higher Level of Abstraction To Transaction • Gate level design is unfamiliar to designer To RTL Systems RTL Gate Gates 0100101110010110 1101011000110110 1000011111000000 Silicon

17. Abstraction Correlation • Silicon signal data is usually easy to assign to gate-level signals • Gate-level netlist and values are difficult for RTL designers to understand and debug • Data must be mapped to the “designers world” for efficient debug and collaboration • One-to-one correspondence is not always the case after synthesis transformations Correlation

18. Abstraction Correlation - Mapping • Name-based mapping • Predefined rule mapping (delimiters, escaped name, naming convention for register, etc.) • Regular-expression-based user-defined renaming rule • Structural dependency analysis • Find structural bounding mappable signal set of name-unmappable signal. • Find structural fanin/fanout intersect of the mapped signal set for related circuit part. • Important concept: granularity (fundamental limitation) and relevance (heuristic). • Name-based mapping should provide a certain percentage of mapped signals for this to work. This could often be achieved after setting some user-defined renaming rules because synthesis tools typically preserve/transform quite well some of the signal naming, especially registers • Other potential techniques can be functional-based correlation commonly used in equivalence checking

19. Abstraction Correlation - Mapping

20. SignalData Open Transactor Interface M1 S1 3X4 2X4 … Data Extraction D11D12D13 S2 M2 DataExtraction D21D22 S3 Data Extraction D31 M3 nTX S4 Abstracting Signal Data to Transactions Transaction visualization eases understanding of communication protocols Addresses sent A1 A2 A3 A … AMBA AXI, AMBA AHB, PCI Express, OCP-IP,UART, DDR, MPEG

21. Results - Correlation

22. Results - Data Expansion

23. Summary • Silicon debug/diagnosis is a bottleneck to time-to-volume • Emerging DFD techniques make data accessible • Silicon data must be expanded and correlated in order for the designer to debug • The proposed method leverage DFD data and make it possible to effectively use HDL-oriented tools for silicon debug HDLDebug SystemValidation