Digital block implementation methodology for a 130nm process

1. Digital block implementation methodology for a 130nm process Microelecronics User Group meeting TWEPP 2009 – ParisSandro Bonacini CERN PH/ESE sandro.bonacini@cern.ch

2. Motivation Implementation of digital blocks for small (~200 kgate) logic cores for digital or mixed signal ASICs Using the IBM 130 nm standard cell library Separate substrate/ground and n-well/VDD biasing for mixed signal designs Defined methodology compatible with mixed signal design flows Open Access based Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

3. Design flow components • Tools • Virtuoso 6.1.3 (OA based) • SOC Encounter 7.1 • Conformal 7.2 • EXT 7.1.2 (QRC) • Assura 3.2 • Calibre 2008.3 • Design Kits • IBM CMOS8RF DM design kit V1.6 • 3 thin, 2 thick, 3 RF metals. • IBM CMOS8RF LM design kit V1.6 • 6 thin, 2 thick metals. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

5. Synthesis • Timing constraints: • Clock definitions • Input delays, fanout, transition, etc. • Output load, etc. Timing constraints [.sdc] RTL description [.v] / [.vhd] Synthesis,mapping andtiming reports Max timing Liberty libraries [.lib] RTL synthesis Capacitance tables [.CapTbl] Abstract layout Definition [.lef] Mapped netlist [.v] Conformal script [.lec] RTL compiler script [.tcl] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

6. RTL Compiler [rc] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

7. Logical Equivalence Checking

8. Logic Equivalence Checking Tool: Conformal Mapped netlist [.v] RTL description [.v] / [.vhd] Conformal script [.lec] Logical Equivalence Checking Max timing Liberty libraries [.lib] LECreport Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

9. Synthesized netlist User RTL code Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

10. Floorplanning & power routing

11. Design import and floorplanning RTL description [.v] / [.vhd] Mapped netlist [.v] Min/Max timing Liberty libraries [.lib] Reports Floorplanning & power routing Capacitance tables [.CapTbl] QX tech file [.tch] • Tool: Encounter Open Access Floorplanned Design [.oa] Open Access Standard cells library [.oa] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

12. Design import Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

13. Floorplanning & power routing Define Chip/core size target area utilization I/O placement module placement in case of TMR or other special constraints Power planning/routing Core/block rings and stripes Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

14. Placement

15. Placement Encounter command file Open Access Floorplanned Design [.oa] Connect cells power/ground Add tap cells Placement Scan-chain reorder Reports Open Access Placed Design [.oa] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

16. Placement Tap cells Standard cells Power/ground connections Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

17. Congestion analysis

18. Congestion analysis Use Encounter Trialroute to estimate congested areas Manually add placement partial blockage Change position of I/Os or blocks …or increase number of routing metals Open Access Placed Design [.oa] Congestion analysis Placement optimization Open Access Placed Design [.oa] Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

19. Timing optimization Clock tree synthesis Timing optimization Routing Timing optimization

20. Automatic P&R steps Open Access Placed Design [.oa] Timing optimization Clock tree synthesis Timing optimization Routing Timing optimization Open Access Routed Design [.oa] Reports Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

21. Clock tree synthesis & signal routing Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

22. DFM Signoff RC extraction Timing analysis

23. Design for manufacturing Open Access Routed Design [.oa] Antenna fix Final netlist [.v] Via optimization Cells & metal fill Open Access Final Design [.oa] Signoff RC extraction Delay file [.sdf] Signal integrity analysis Signoff timingreport Timing analysis Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

24. Antenna fix Re-routes long nets Inserts tie-down diodes Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

25. Via optimization Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

26. Cells & metal fill Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

27. Timing closure If signoff timing analysis reports violations increase buffer sizes add extra buffers reroute signals check constraints exploit useful skew annotate native post-route RC extraction tool re-run optimization Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

28. Logical Equivalence Checking DRC LVS

29. Virtuoso OA design is present in Virtuoso Easily included in a mixed-signal chip Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

30. Thank you… Design flow …is soon to be available Implementation of digital blocks Using the IBM 130 nm standard cell library Defined methodology compatible with mixed signal design flows Open Access based Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch