Fast A/D sampler FINAL presentation

1. Presented By: Tal Goihman, Irit Kaufman Instructor: MonyOrbach Winter 2012 Fast A/D sampler FINAL presentation

2. Goals • Project Goal: • Design and implement an A/D system using Xilinx Virtex6 development board for sampling at highest possible rate. • Sample to virtex6 development board DDR memory. • Transfer the sampled data to PC memory through PCIe and save the data to disk.

3. ML605 development board FMC125 Fast A/D FMC Conn H/W Block Diagram DDR3 A/D IC Virtex6 FPGA PCI-E Connector PC

4. MicroBlaze UART ADC Control Implemented In XPS Timer Aggregator FMC125 AXI Master DDR3 Memory Controller (MIG) AXI Slave PCI Express AXI Slave CDMA Implemented In ISE project Navigator AXI Master Mailbox “wormhole” AXI4 AXI4-lite Design Block Diagram

5. Block Diagram: Main Data Channel Aggregator AXI Master DDR3 FMC125 Memory Controller (MIG) AXI Slave • FMC125 delivers data using 4 128-bit lanes of a proprietary bus running at 125Mhz into the aggregator. • Aggregator unites and synchronizes the different channels into a 512-bit bus. • AXI Master sends the data over a 256-bit wide AXI bus running at 200Mhz to the AXI Slave interface of the Memory Controller. • Memory controller handles Writes to DDR3. • FIFO’s and H/W Flow control in every component throughout the channel to achieve highest possible bandwidth. Achieved 5.13GB/s, 82% utilization out of theoretical 6.25GB/s. • Throughput is measured using a timer from the start of the write operation until assertion of a write done signal from the AXI master

6. Block Diagram: memory to PCIe • After the data is sampled to memory the system transfers the first chunk to the Host PC’s DMA buffer. • The subsequent chunks are transferred upon receiving a command from the Host PC. • Data is read from memory and transferred to PCIe by the DMA engine • Throughput was matched to PCIe • Transferred in 16MB chunks (the chosen DMA buffer size) • Address translation occurs in the PCIe core