SoC Architecture Course Oct 2008 – Jan 2009, KTH

1. SoC Architecture CourseOct 2008 – Jan 2009, KTH Zhonghai Lu / Axel Jantsch zhonghai@kth.se

2. Course Information • Course responsible: Dr. Zhonghai Lu • Course examiner: Prof. Axel Jantsch • 12 Lectures, 4 Tutorials, 3 Labs • Home page: www.ict.kth.se/courses/IL2207 • Course Material • Dally, Towles: Principles and Practices of Interconnection Networks • Distributed Material • Slides • Advanced-level course, more demanding SoC Architecture

3. Lecture Overview • L1: Introduction • L2: Buses and Arbitration (Dally: 22, 18) • L3: Shared Memory Multiprocessors • L4: Cache Coherency Protocols • L5: Memory Consistency • L6: Introduction to Network-on-Chip, Topologies (Dally: 1, 2, 3, 4, 5) • L7: Routing Algorithms and Mechanics (Dally: 8, 9, 10, 11) • L8: Flow Control (Dally: 12, 13) • L9: Deadlock and Livelock (Dally: 12, 13, 14) • L10: Router Architecture and Network Interface (Dally: 16, 17, 20) • L11: Quality of Service and Performance Analysis (Dally: 15) • L12: Course Summary and Trends SoC Architecture

4. Tutorial Overview • T1: Bus, arbitration and cache coherency • After Lecture 5, on Nov. 5 • By Prof. Jantsch  • T2: Memory consistency and network topology • After Lecture 7, on Nov. 12 • By Dr. Lu • T3: Interconnection networks (routing, flow control, deadlock etc.) • After Lecture 8, on Nov. 19 • By Dr. Lu • T4: Router architecture, QoS and performance analysis • After Lecture 12, on Dec. 3. • By Prof. Jantsch SoC Architecture

5. Lab Overview • Laboratory 1: Uniprocessor SoC Design with Altera • Laboratory 2: Multiprocessor SoC Design with Altera • Laboratory 3: Wormhole Networks • Students work in groups of max. 2 • Good preparation is required. SoC Architecture

6. Course Requirements To pass the course the student has to fulfill the following requirements: • Pass the final exam. The grade for the exam will be the grade of the course. • Final exam: Dec. 16, 2008, 9:00-13:00, Room 432, 438, 439,530 • ** Register the exam in Daisy 2 weeks before the exam date in order to guaranttee a seat *! • Attend tutorials • Complete all labs SoC Architecture

7. Observations in System Design

8. Intel 4004 (1971) 108 KHz 2,300 transistors If automobile speed had increased similarly over the same period, we could now drive from Stockholm to Shanghai in about 23 seconds. Advances in Integration Intel Pentium 4 (2000) 1.5 GHz 42 million transitors SoC Architecture

9. Advances in Integration - 2007 • Intel Terflop Chip 2007 • http://techresearch.intel.com/articles/Tera-Scale/1449.htm

10. Moore’s Law: Standard cell density and speed Design Productivity Crisis Potential Design Complexity and Designer Productivity 10,000 10,000 100,000,000 Equivalent Added Complexity 1,000 10,000 Logic Tr./Chip 58%/yr compounded Complexity Growth Rate Tr./S.M. 1,000 100 100 10 1,000 Density (Kgates/mm2)ASIC clock (MHz) Logic Transistor per Chip (M) 10 1 Productivity (K) Trans./Staff – Mo. 21%/yr compounded Productivity Growth Rate x x 1 0.1 x x x x x x Gates 0.1 0.01 Clock 0.01 0.001 100 2009 2013 2001 2003 2005 2007 2011 2015 1985 1989 1987 1983 1991 1993 2009 1981 1995 1997 2007 1999 2001 2003 2005 Source: (SRC 1997) Growing Design-Productivity Gap Designs do not only get more complex, but also much more expensive! SoC Architecture

11. The Role of the Market! Source: Smith 1997 SoC Architecture

12. RTL function 1 Processor RTL function 2 RTL function 3 Yesterday’s SOC Memory RTL I/O RTL RTL RTL Ctl Proc RTL RTL RTL RTL RTL Today’s SOC RTL Mem RTL RTL RTL RTL RTL DSP RTL I/O RTL RTL Mem Moore’s Law drives the development of System-in-Chip Architectures The growing number of transistors on an SOC drives the trend towards more RTL blocks on the chip Source: Leibson (DAC2004) SoC Architecture

13. Verification Costs • The percentage of the verification costs of the total design costs is continuously increasing (at present 50-70% for large designs) SoC Architecture

14. Platforms reduce Costs SOC Flexibility = Per-Unit Cost Reduction (Model: 100K and 1M system volumes) Source: Leibson 2004 Low-endstill camera High-endstill camera Total per unit cost Video camcorder System designs per chip design One Chip Many System Designs $10M design cost, $15 manf. cost, 5% premium for programmability SoC Architecture

15. Platform Example: Nexperia SoC Architecture

16. Nexperia Instance: Viper SoC Architecture

17. Arm based MPSoC Platform SoC Architecture

18. Texas Instruments OMAPA SOC Platform based on Peter Cumming: ”The TI OMAP Platform Approach to SOC”

19. The OMAP platform • OMAP products are combinations of hardware and software allowing mutimedia capabilities to be included in 2.5G and 3G wireless handsets and PDAs • Critical design paramters are: Performance, Power, Cost and Time-to-Market • First Approach: ”Opportunistic Reuse” • No planned reuse, but try to reuse whenever possible • Second Approach: ”Structured Approach” • Systematic Reuse, SoC Platform SoC Architecture

20. What is a platform? • OMAP defines a platform as • ”a packaged capability used in subsequent stages of the development to reduce development costs” • Platforms have the following characteristics: • Between silicon and systems many platforms may be developed and used in subsequent stages of the development • Platforms are valuable due to the notion of reuse (good for economy) • They include hardware, software, assemblies and tools! SoC Architecture

21. Examples for platforms • Transistor and ASIC libraries are the lowest hardware platforms • Instruction Set Architecture and associated Assembly Language Tools are the lowest levels in Software • These well-understood levels are used by other OMAP platforms SoC Architecture

22. OMAP: Hierarchy of Platforms • OMAP uses platforms on different levels • This is a precondition for reuse Application Specific Ref Design Appl. Platform OMAP Products OMAP Infrastructure SoC Platform ASIC Library & Tools Reuse Silicon Technology SoC Architecture

23. SoC Platform • The SoC platform consists of • A library of hardware components • An architecture for their interconnection • The Application Platform (the OMAP product) • Processor and Peripherals • Low-Level Software (Drivers) • Development Environment • The System Platform • The platform includes the code that controls all aspects of the system from device driver to system interface • TI has a reference design group in order to understand the new demands for OMAP SoC Architecture

24. OMAP Products • The OMAP product range consists of several families of devices for different markets, e.g. • Application processors for 3G: OMAP 1510 and 1610 • Application processors for 2.5G: OMAP 710 and 730 SoC Architecture

25. OMAP 1510 • OMAP 1510 is based on • Enhanced ARM 925 core (RISC processor) • TI C55x core • DMA, SRAM, Busses, Peripherals SoC Architecture

26. Current OMAP platform for Wireless Handset & PDA • OMAP™ 3 architecture combines mobile entertainment with high performance productivity applications (Source: Texas Instruments) SoC Architecture

27. Strength of the OMAP concept • The main strength of the OMAP concept is that several actors can make extensive Reuse of development efforts at several levels of the design process • Actors: • Mobile Device Manufacturers • Software Developers • TI’s internal Development Teams • Levels: • Common Hardware and Software Interfaces • Common Development Environment • Single Low-Level Software Framework (Code can be used for several products) • Single SoC Platform • OMAPI is an interface standard for OMAP founded by TI and ST SoC Architecture

28. OAMP Architecture • The OMAP architectute consisting of general purpose processor and DSP has been chosen because of the application area • Need for Performance • Energy and Area Constraints • Two Main Tasks: User Interface and Signal Processing • Flexibility and Reuse SoC Architecture

29. Requirements on Software Platform • Hardware architecture requires a matching software approach • Well-defined Set of Application Programming Interfaces in the high-level OS running on the general purpose processor • System Software that links General Purpose Applications to DSP components • Well-defined Standard for DSP Components (TMS320 Algorithm Standard or eXpressDSP) SoC Architecture

30. Summary • The OMAP platform • Covers a wide range of products allowing to reuse Hardware and Software • Hardware Architecture adopted to Application Area • Software Architecture using features of Hardware Architecture • Efficient SOC Platform with Definitions for Hardware and Software Reuse SoC Architecture

31. Emerging Architectures

32. Memory FPGA Micro- controller Analog- Digital Digital- Analog Communication Structure Custom Hardware DSP System-on-Chip Architectures • A system-on-chip architecture integrates several heterogeneous components on a single chip • A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead SoC Architecture

33. Memory Micro- processor DSP Custom Logic I/O System-on-Chip Architecture:A bus-based SoC System on a chip SoC Architecture

34. System-on-Chip Architecture: Network-on-Chip Switch • The resources are connected to the network via network interfaces • The topology of the network and the capability of the switches and communication channels determines the capacity of the network PE3 PE1 NI NI Resource Channel PE2 MEM NI NI Network Interface SoC Architecture

35. ASIC Technologies

36. What is an ASIC? • ASIC = Application Specific Integrated Circuit • An ASIC is an integrated circuit for a specifc application and (generally) produced in relatively small volumes. • An ASIC-technology helps to shorten the design time by providing a semi-fabricated integrated circuit SoC Architecture

37. Programmable Logic Programmable Logic Device (PLD) Field Programmable Gate Array ASIC Standard Cell Gate Array ASIC families The term ASIC is often reserved for circuits that are fabricated in a silicon foundry, while circuits that can be programmed at the customer’s site are called Programmable Logic. The term full custom is reserved for circuits where all silicon layers can be optimized. This implies a long design process and thus full custom is mainly used for high-volume high-end circuits. SoC Architecture

38. Standard Cell • Standard cells are often referred as Cell-Based Integrated Circuits (CBIC) • All mask layers are customized • The standard cell library defines logic elements of varying complexity: SSI, MSI logic, data path blocks, memories and system-level blocks. SoC Architecture

39. Standard Cells • Cells are configured in rows and have constant height and variable width • Each cell is optimized for an efficient implementation SoC Architecture

40. Gate Array • A gate array chip contains prefabricated adjacent rows of PMOS and NMOS transistors • The gate array is configured by the interconnect structure SoC Architecture

41. Channeled Gate Array • Only the interconnect is customized • The interconnect uses spaces between rows of base cells SoC Architecture

42. Channelless Gate Array(Sea of Gates) • Only the interconnect is customized • Cells are connected via unused transistors SoC Architecture

43. Field Programmable Gate Arrays • None of the layers are customized • Basic logic cells and interconnect can be programmed • Basic cells can be SRAM based, Flash Memory based or fuse-based (one time programmable) SoC Architecture

44. Programmable Logic Device • No customized mask layers or logic cells • A single large block of interconnects • Macrocells consist of programmable array logic followed by a flip-flop or latch SoC Architecture

45. Comparison FPGA, Gate Array, Standard Cell SoC Architecture

46. Design Trade-Offs Design Time Full Custom Standard Cell Gate Array Programmable Logic Microprocessor Performance SoC Architecture

47. Challenges for System Design

48. Design Product (Implementation) How to design a system-on-chip? Idea (Specification) • Specification • Design productivity increases with the level of abstraction • The task of functional verification is very difficult at low abstraction levels abstract Abstraction Gap • Implementation • Efficient implementations require to exploit the low-level features of the target architecture detailed Challenge for System Design! SoC Architecture

49. SoC Design • The continuous progress in silicon process technology allows to increase more and more functionality on a single chip => Systems on a chip become reality • Market-driven forces: • Shorter product design schedules and life spans • Products have to confirm to standards • The design has to be right from the start. An implementation error means heavy loss of money or product death • Large designs are integrated into a single chip The SoC design process must address these driving forces SoC Architecture

50. Design Step Abstraction Gap Intermediate Model Design Space The Design Process Design Specification Abstraction Level Implementation SoC Architecture