Being Assertive With Your X (SystemVerilog Assertions for Dummies: version 2013)

1. Being Assertive With Your X (SystemVerilog Assertions for Dummies: version 2013) Don Mills Microchip Technology Inc, Chandler, AZ, USA don.mills@microchip.com mills@lcdm-eng.com

2. Outline The Origin of X The Big Lie - If you don’t see it, it isn’t there. The Old-Fashioned solution The tool kludge being promoted today Using SystemVerilog assertions to seek out your X SystemVerilog assertion bind Conclusions and Recommendations Mentor’s Best Kept Secret Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

3. The Origin of X • Floating input ports • Gate level X’s • timing violations • UDP • UPF – low power mode • Out of range bit-selects and indices • Uninitialized Variables (4-state types) • Flip-flop data path chain • Follower Flops • Uninitialized flops and latches • Multiple drivers on a wire • without a tri-state driver • Direct X assignment • Undriven wires Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

4. The Big Lie • Designers focus on functionality • Seldom is RTL coded with integrity checkers • Code that blocks or hides X’s : • if/else statements • case/casez/casex/caseinsidestatements • combinational logic • and/or logic • ternary operator “ ? : ” Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

5. if/else statements X-hiding • One of the most common X-hiding statement is an if/elsestatement always_comb begin if (sel) out = a; else out = b; end The if will be true if sel is true (1’b1) The else condition will execute for all other values of sel (1’b0, 1’bX, 1’bZ) Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

6. case statements X-hiding • For standard case statements (NOT casez, casex, or case inside) logic [1:0] sel; logic a, b, c, d, out; always_comb case (sel) 2'b00 : out = a; 2'b01 : out = b; 2'b10 : out = c; 2'b11 : out = d; endcase when the case expression has an 1’bX (or a 1’bZ) it’s value will be lost and the case statement will hold it’s previous value Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

7. casex, casez, case inside statements X-hiding • casex, casez, case inside statements apply “don’t-care” mapping to X’s and Z’s. When the case expression has an 1’bX (or a 1’bZ) it will be treated as a don’t care for casex and casez. When the case items have X’s or Z’s they will be treated as don’t cares for casex, casez, caseinside. (lots of SV rules not discussed here) logic [1:0] sel; logic a, b, c, d, out; always_comb casex (sel) 2'b00 : out = a; 2'b01 : out = b; 2'b1X : out = c; 2'bZ1 : out = d; endcase Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

8. if / else vs. conditional operator for X- propagation • Many use the conditional operator (thinking it will always propagate X’s) – wrong! always_combbegin if (sel) out = a; else out = b; end assign out = sel ? a : b; OR always_comb out = sel ? a : b; sel a b out 0 dead beef dead 1 dead beef beef X dead beef xexx X dead deaddead sel a b out 0 dead beef dead 1 dead beef beef X dead beef beef BOTH methods will prevent X propagation

9. and/or expression X-hiding • Anything and’ed with a low will output a low • Anything or’ed with a high will output a high logic a, b, c, d, out1, out2; assign out1 = a & b; assign out2 = c | d; logic a, b, c, d, out1, out2; and (out1, a, b); or (out2, a, b); Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

10. The Old-Fashioned Solution • Add extra condition checking in the middle of the RTL functional description • Add $display statements in RTL functional code • Hide these display statement from synthesis using pragmas • Very cumbersome to code and maintain and therefore rarely used Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

11. Verilog Manual Assertion always_comb if (sel == 1’b1) out = a; else //pragma translate off if (sel == 1’b0) //pragma translate on out = b; //pragma translate off else // sel == 1’bX or 1’bZ begin out = 'x; $display(%m "assert: sel X or Z at time %d“, $time); end //pragma translate on always_comb if (sel)out = a; else out = b; Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

12. Changing the rules? always_comb if (sel)out = a; else out = b; • Some simulators provide an X-propagation/X-optimization option • The X-propagation mode: changes the RTL rules and propagates an X out even if a and b are known • The X-optimization mode: If all the data inputs are the same value, that value will be propagated Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

13. Find your X with SV Assertions • Using immediate assertions is a simple method to monitor for X in a design. • They can be applied within a functional module. • To monitor combinational if/else, case, and continuous assign statements. • They can be applied at the test bench level. • For ports and flip-flop outputs, this method should be considered, since it could be applied to the design both before and after synthesis. • They can be disabled • Severity levels available for reporting • Automatically ignored by synthesis Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

14. System Verilog Immediate Assertions Syntax assert (expession) pass_statement(s) [elsefail_statment(s)] • For syntax for SystemVerilog immediate assertion • SystemVerilog built-in severity levels • $fatal - ends the simulation • $error - gives a runtime error, but simulation continues • $warning - gives a runtime warning, simulation continues • $info - prints the specified message Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

15. SystemVerilog Assertions if/else statement always_comb begin assert (!$isunknown(sel)); if (sel == 1’b1) out = a; else out = b; end always_comb begin assert (!$isunknown(sel)) else$error(“%m, sel = X”); if (sel == 1’b1) out = a; else out = b; end Simple immediate expression using default error statement Example with error message included Could use a ‘define macro for the assertion code or SV “let” statement Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

16. Use macro’s with arguments `defineassert_X(arg) assert (!$isunknown(arg)); always_comb begin `assert_X(sel) if (sel == 1’b1) out = a; else out = b; end `defineassert_X(arg, msg=“”) \ assert (!$isunknown(arg)) \ else$error(“%m,%s”, $time, msg); always_comb begin `assert_X(sel,”sel=X”) if (sel == 1’b1) out = a; else out = b; end Replace the immediate assertion with a `define macro Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

17. SystemVerilog Assertions case statement always_comb begin `assert_X(sel,”sel=X”) case (sel) 2'b00 : out = a; 2'b01 : out = b; 2'b10 : out = c; 2'b11 : out = d; endcase end Don Mills, Microchip Technology, Being Assertive with Your X, April 2013 always_comb begin assert (!$isunknown(sel)) else$error(“%m, case sel = X”); case (sel) 2'b00 : out = a; 2'b01 : out = b; 2'b10 : out = c; 2'b11 : out = d; endcase end

18. SystemVerilog Assertions continuous assignments always_comb begin `assert_X(x_check,”comb_logic=X”) end OR Don Mills, Microchip Technology, Being Assertive with Your X, April 2013 assign out_or= a | b; assign out_and = c & d; assign out_tern= sel ? e : f; assign x_check= {a,b,c,d,e,f,sel}; always_comb begin assert (!$isunknown(x_check)) else$error(“%m, comb_logic = X”); end

19. SystemVerilog Assertions for GLS as well as RTL • Ports and flip-flop output names are preserved through synthesis • At least a some variation of a flip-flop output name is preserved. • Recommendation • Put assertion X checks for ports and FF’s in a side file that is then bound to the design Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

20. SystemVerilog Assertions Port check example modulePortCheck(input logic in1, in2, din, clk, out1, out2); logic [5:0] sig_list assignsig_list = {in1, in2, din, clk, out1, out2} `assert_X(sig_list),”X in foo ports”) endmodule Don Mills, Microchip Technology, Being Assertive with Your X, April 2013 modulefoo(input logic in1, in2, din, clk, output logic out1, out2); assign out1 = in1 & in2; always_ff@(posedgeclk) out2 <= din; endmodule

21. SystemVerilog Assertions Port check example Cont’ • Bind is like a local instantiation Module PortCheck (instance X_ports) will be pseudo-instantiated into module foo Don Mills, Microchip Technology, Being Assertive with Your X, April 2013 module top; logic in1, in2 ... foo f(.*) test tb(.*) bindfooPortCheckX_ports (.*); ... endmodule

22. Disabling assertions • X checking for assertions are not always welcome • During boot-up • UPF low power mode • SystemVerilog Assertions built in system tasks disable/enable assertions • $assertoff and $asserton • Arguments to $assertoff and $asserton allow the user to specify • A list of assertions • A list of modules • A hierarchy depth (levels down the hierarchy) Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

23. Conclusions &Recommendations BUT WAIT, There’s more: Mentors best kept secret • SystemVerilog assertions for X detection • easy to use • built into the language • ignored by synthesis • can be turned on and off real time during simulations. • Use SystemVerilog assertions to monitor for X’s • check all conditional tests, IE. if (sel) or case expression • check all inputs and/or outputs of module • Assertion checks are better than tool based X-propagation hooks • they tell where the problem starts • (could be automated by the tools) Don Mills, Microchip Technology, Being Assertive with Your X, April 2013

24. MENTOR’s Best Kept Secret

25. Concurrent Assertion with chained implications 0 1 2 3 4 5 6 7 9 10 8 a b c d p_chain property p_chain; @(posedge clk) $rose(a)|-> b[*0:$] ##1 c |-> d; endproperty:p_chain; ap_chain: assert property (p_chain); Does not end with a pass at cycle 4 or cycle 7 If Chained Implications in Properties Weren’t So Hard, They’d be Easy, Oct 2009

26. Another look… property p_chain; @(posedge clk) $rose(a)|-> b[*0:$] ##1 c |-> d; endproperty:p_chain; ap_chain: assert property (p_chain); Why doesn’t this assertion end here with a pass when both c and d are high? Why does this assertion end with a pass here? If Chained Implications in Properties Weren’t So Hard, They’d be Easy, Oct 2009

27. Assertion Thread Viewer (ATV) Assertion statement is listed at the top of the window Pass/Fail for tested signals is noted for each time step Only one Assertion thread is listed at a time Self taught – documentation is outstanding for this tool ATV must be enabled for a given assertion and a specific thread of that assertion prior to running a simulation If Chained Implications in Properties Weren’t So Hard, They’d be Easy, Oct 2009

28. Concurrent Assertions Use Special Event Scheduling • Concurrent assertions use special event scheduling queues • Prevents race conditions with events in the design modules

29. Why Use the ATV (Mentor’s Best Kept Secret) • Concurrent Assertions are sampled at the beginning of a time step • If data is changing during the time step • Must look at the data prior to the time step • Like a D-FF – must look at the value of D prior the clk edge • ATV doesn’t show the value, it shows the pass/fail for each time step If Chained Implications in Properties Weren’t So Hard, They’d be Easy, Oct 2009