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Electrical Architecture and Interfaces

Electrical Architecture and Interfaces. Pierre PRAT Progress Meeting @APC the 12.10.2012 Michel DUPIEUX. Grounding. Grounding Design is now stable after Johan Panh’s Remarks. Grounding principles. In order to avoid ground loops: Use of galvanically isolated DC/DC converters

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Electrical Architecture and Interfaces

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  1. Electrical Architecture and Interfaces Pierre PRATProgress Meeting @APC the 12.10.2012 Michel DUPIEUX

  2. Grounding • Grounding Design is now stable after JohanPanh’s Remarks

  3. Grounding principles • In order to avoid ground loops: • Use of galvanically isolated DC/DC converters • Primary grounds (28V Battery) shall be connected on Mechanical ground of PWP • Secondary grounds of DC/DC converters shall be connected on a single point on Mechanical ground of sub-equipments (DP, PDM) • Mechanical grounds connected together • Differential links (LVDS) between HK, CCB and PDM_Board, HVPS-1

  4. Harness shielding • According to the recommendations of Johan Panh: • Primary power supplies : twisted pairs, not shielded • Secondary power supplies : • LVPS-PDM <==> PDM_Board : twisted pairs, shielded, with shielding connected to mechanical ground (360°) on each sides (HF immunity) • HVPS-1 <==> HVPS-2 : twisted pairs, shielded, with shielding connected to mechanical ground on HVPS-1 side and open on load (BF immunity) • LVPS-HK, LVPS1-DP, LVPS2-DP <==> HK, CCB, CLKB, GPSR, CPU, DST: twisted pairs, not shielded (TBC: internal connection of DP) • Differential digital links: twisted pairs, shielded, with the shielding connected to mechanical ground (360°) on each side

  5. HVPS-1 - HVPS-2 - HK - PDM-Board Interface Synoptic : 1st flight version 28V (S) BAT_RET (P) 1 GND_28V (S) 3.3V (S) 28V_BAT (P) 2 GND_3.3V (S) D-Sub 9 F D-Sub 9M D-SUB 25 F D-SUB 25 M 6 C-W 3 C-W 6 x 14 HV lines 3 ON/OFF 3 0-2.44V 3 STATUS 4 SWITCHCOMMANDS 3 x 14 HV lines HVPS-2 HVPS-1 CS_DAC CS_DAC MOSI 6 SCK 3 MOSI 0-2.44V 6 DAC 3 DAC CS_OUT SCK CS_IO 9 6 bidirectional signals ON/OFF I/O expanders MOSI MISO 9 6 status signals D-Sub 9M SCK STATUS D-Sub 9 F Interrupt 4 SWITCHCOMMANDS MOSI MISO SCK Interrupt 2 2 2 2 2 2 2 2 2 2 2 differential transmitters GND_M 4 differential receivers 4 differential receivers GND_M BATTERY 24 wires D-Sub 15 F 6 Differential signals (LVDS) ( x2 = 18 wires)between HK and HVPS-1 D-Sub 15 M 4 Differential signals (LVDS) ( x2 = 8 wires)between PDM_Board and HVPS-1 Micro-D 9 M D-Sub 15 M D-Sub 15 F Micro-D 9 F GND_M HK PDM_Board 4 differential transmitters HVPS-1 would have DC/DC converters to isolate the powers 4 differential transmitters 2 differential receivers

  6. HVPS • Architecture and I/F are now stable: • 2 HVPS boxes in PDM box: • HVPS-1: • 2 CV DC/DC (28V & 3.3V) for ground isolation • SPI I/F with HK, • LVDS I/F with PDM-Board (switch pulses), • 3 DACs (HV tuning), • 3 Cockcroft-Walton Converters. • HVPS-2: • 6 DACs (HV tuning), • 6 Cockcroft-Walton Converters.

  7. Subd25 or 37? Subd25 or µSubd9? HK • Electrical Interfaces are clearlydefined (connectors, pinout Ok)

  8. DP Block Diagram

  9. DP connectors ? • Pinout and connectorsneed to bechecked and update verysoon

  10. PDM Power connections PDM BOARD Connector PDM_EC_ASIC 3.3Va_EC (S) EC-ASIC TES 1-0511V GND_3.3Va_EC (S) 3.3Vd_EC (S) LVPS-PDM Connector PDM-LVPS GND_3.3Vd_EC (S) 5V_EC (S) 1.5V_EC (S) GND_5V_EC (S) GND_1.5V_EC (S) Regulator EC_ASIC 1 GND_M GND_1.5V_EC should be linked to the gnd of the FPGA 5V_PDMB (S) FPGA 1V GND_5V_PDMB (S) 1.8V FPGA ground should be linked to the GND_M 1.5V 3.3V GND_M • Pinout and connectorsbetweenPDM_Board and EC_Asic are checked

  11. Interfaces with: • CCB µSubd51 • HVPS µSubd9 • HK µSubd9? Subd25 on HK? • POWER Subd9 120 pins PDM ASIC A ASIC B ASIC C ASIC D ASIC E ASIC F A B C D E F 68 pins 68 pins 68 pins 68 pins 68 pins 68 pins Fixation screw EC_HV Kaptoncable MAPMT

  12. PWP PWP-outside 9 pins Sub-D connector PWP2-Outside Power 22W??Which dimensions PWP1-Inside Power 250 W ?? All connectors on a single side To IR-CAM To LVPS-DP1 LVPS-DP2 LVPS-PDM LVPS-HK HVPS1 Plus twoadditional PWP-Inside

  13. PWP Componant Battery Cells,Connectors and Cables • Cells • Connectors • Cables • Option I: In case of 90W powerconsumptionitwillbenecessary 20 cells of Saft G62/1.2 • Option II: In case of 250W powerconsumptionitwillbenecessary 50 Cells of Saft G62/1.2 The Connectors we are going to use are 9 pins D-Sub connectors for all interfaces and subsystems. The Cables we are going to use are THERMAX MIL-DTL-22759/91,92 for all interfaces and subsystems.

  14. PWP Power Budget ?? • 250W • 90W Total Power Budget: 74W+20% of Security Margin = 90W Total: 111.2W+20% of security Margin = 133.4W Additional Heaters and backup = 70W (150+60)+20% of security Margin = 243.6W Thisversionshouldbediscussed • Whichcongiuration for Baseline? • Which power for Pack2 for IR Camera?

  15. Femealeconnector? Short circuit risk? PWP • Femealeconnector on power side • PinOut of External Power • Common Ground or GroundSwitching ? • Pinout Compatibility withLVPSsand HVPS1 ? • IR Camera the samewaywithseparateBattery? • WhoProvidesMaterial and cables?

  16. SIREN HK 232/422 DP • Electrical Interfaces are clearlydefined (connectors, pinout Ok)

  17. Cables • Whoprovidecablesbetween: • HK and SIREN ? • HK and DP ? • PDM and DP ? • DP and SIREN ? • PWP_1 and LVPS (4)? • PWP_1 and HVPS_1? • LVPS_PDM and PDM? • HK et HVPS_1? • PDM_and HVPS_1? • CCB and PDM_board? • HK et PDM Board? • IR Camera ?

  18. ToDo • Which Power budget PWP_1 ? • Clarify Power Pack interfaces. • Whoprovides Batteries (PowerPack 1 and Power Pack 2 ? • Clarifyinternal and external interfaces for DP (update Synoptic). • Definecables, providers ? • Use in generalFemealeconnector on Fixed on boxes exept for power side to avoid short circuit risk!!! • Documentation

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