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Electrical/Optical Issues in I/O CMOS Interfaces

Electrical/Optical Issues in I/O CMOS Interfaces . Thad Gabara Bell Laboratories Murray Hill, NJ. Electrical vs. Optical. Interconnect length is a limiting aspect on-chip between chips between boards between cabinets between buildings cities and countries. thrend/BW. Electrical.

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Electrical/Optical Issues in I/O CMOS Interfaces

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  1. Electrical/Optical Issues in I/O CMOS Interfaces Thad Gabara Bell Laboratories Murray Hill, NJ Optical Interconnect Workshop

  2. Electrical vs. Optical • Interconnect length is a limiting aspect • on-chip • between chips • between boards • between cabinets • between buildings • cities and countries thrend/BW Electrical Optical Optical Interconnect Workshop

  3. Rent’s Rule 10K ASIC #I/O = k np 0.2 < p < 0.7 3 < k < 4 1K Processor I/Os 100 Memory ISD June 1998, Tets Maniwa 107 108 109 1010 1011 1012 transistors (n) Optical Interconnect Workshop

  4. Chip Interconnect Density 5000 4000 I/Os per die solder bump - 225mm 3000 2000 Wire bond - 70mm 1000 Wire bond - 100mm 6 8 10 12 14 16 IBM, M. Nealon, Micro News Die size (mm2) Optical Interconnect Workshop

  5. 3 2.5 2 1.5 1 Chip to Board Clock Rate Multiplexed Bus Clock rate (GHz) Peripheral Bus Source: SIA 1997 Roadmap 00 95 05 10 Year Optical Interconnect Workshop

  6. I/O Impact of Scaling CMOS • Density in core is increasing • Allows more data to be processed • Need to keep up information • transfer to/from core • I/O transfer rates increasing • Rent’s rule forces high pin count Optical Interconnect Workshop

  7. Wire bond Solder bump Chip I/O Limitation • Solder bump • Process and packaging step differences • CAD tools for chip partitioning • Offers new potentials for system growth • Allows for optimized process attachment Optical Interconnect Workshop

  8. Solder Bump System Possibilities Bi-CMOS CMOS Memory Passives • Shingling die • Combine different optimized • die together • Allows formation of compact • systems Optical Interconnect Workshop

  9. CMOS Chip Optical Chip Communication • Process added step to CMOS • SEED, VCSEL needs to cost compete • with solder bump • May offer backplane benefits • Current High BW interfaces may benefit • CPU-memory • Switching networks Optical Interconnect Workshop

  10. CDR Background • single interconnect • - coding schemes • - contains both clock and data • - bandwidth efficient connection • at destination • - perform post-processing • to extract clock from data • synchronize data at destination • - using recovered clock Optical Interconnect Workshop

  11. CMOS nMOS Bipolar GaAs BiCMOS Clock and Data Recovery Performance Trend projected Sonet target 10 1 data rate (GB/s) 0.1 • Source: International Solid-State Circuit • Conference 80 90 00 Year Optical Interconnect Workshop

  12. 0 7 s w d w s s s d Gate silicon shadowing effect s s d w s d s w Shadowing die outline gate • Digital ASIC technique • Use same layout around the frame • Typically use a linear layout • Small swing buffers are a problem gate Measured Data of Vol of 800mV swing(over several lots) Avg DV s linear 136mV 31.6mV Optical Interconnect Workshop

  13. s 0 7 d s s w Gate s w silicon shadowing effect s s s w d s w Rotational Symmetry die outline gate • Current matches • Gate segments match Measured Data of Vol of 800mV swing(over several lots) Avg DV s linear 136mV 31.6mV Rot Sym 30mV 8.9mV gate Optical Interconnect Workshop

  14. Power LP LS I/O Chip LG Package Packaging • Need to get power/ground to the chip PGA 100 mil pitch 25% Area PGA 100 mil pitch 40% Area BGA 50 mil pitch VL = L di/dt introduces Ground Bounce 60% Direct Chip attach 20 mil pitch IBM, M. Nealon, Micro News Package size reduction achieves: Lower L ; smaller board area. Optical Interconnect Workshop

  15. Rt C N C C NC C RC N RG NC K L K Ground Bounce Reduction Equ Model enable L K Wide Bus i • PVT makes Rt+/- 50% VL = L di/dt • Want to dampen the circuit • Use transistor sizing to control • transistor impedance - RC • Insert impedance in VSS pad and • inverse regulate ground • impedance - RG Optical Interconnect Workshop

  16. n pad data selector Digital Transistor Sizing • Technique used over 2Gb/s • Data path segregated from control • Selector allows dynamic transistor sizing • PVT (Process, Voltage, Temp) compensated (R and I) • Controls impedance, performance, power, etc. • Used in Ground Bounce buffers, HSTL and other buffers Optical Interconnect Workshop

  17. Vamp Vcm N C Test Setup to Measure Bit Errors From Pulse Generator 10MHz (0-3.6V) From BERT Ground Bounce Test Chip 80Mb/s (215-1) Old or New To BERT N N 0 16 60 C C (pF) 0 60 60 Optical Interconnect Workshop

  18. 60 old 60 new 16 old 16 new no activity Bit Errors Generated 1B 100M 10M 1M 100K Number of bit errors (OUT OF 4.8b BITS) 10K 1K 100 7 orders of improvement 10 0.8 0.7 0.9 1.0 0.1 1.1 0.2 0.4 0.3 0.5 0.6 1.2 Vamp (volts) Optical Interconnect Workshop

  19. Computer/mProcessor Trends 100B • Connection • Machine 10B 1B • CRAY XMP-4 • RCA GaAS • CRAY I 100M • AMDAHL • 5860 • CDC 7600 • VAX 8800 • IBM 801 • CDC 6800 • AM2900 • CRISP • IBM 3081 10M • CDC 6600 • CLIPPER • IBM 3033 • IBM 360/85 • WE32200 • WE32100 Instructions/sec • IBM STRETCH • MC68020 1M • MC68000 • VAX 8200 UNIVACI • IBM 7090 • INTEL • 8086 100K • IBM 704 • INTEL • 4004 • INTEL • 8080 EDVAC • WHIRLWIND 10K ILLIAC MARK II COLOSSUS ENIAC 30 TONS 1K COLOSSUS 100 HARVARD MARK I 10 40 50 60 70 80 90 00 Year Optical Interconnect Workshop

  20. Optical Chip Clocking • Process added step to CMOS - maybe? • Reduces skew • Easier to synchronize chip CMOS Chip Optical Interconnect Workshop

  21. Atten Freq 100MHz Skin Effect d = (pfms)-0.5 • Skin effect • Affects the cross-sectional area • The high-frequency components become • more attenuated • This causes “pattern dependent” effects which • is know as intersysmbol interference T Below some T, the eye diagram of the data degrades in W and H H W Optical Interconnect Workshop

  22. Optical Communication • Skin effect doesn’t occur • Attenuation - 0.2db/km? • Electrical attenuation -5db at a few GHz • Electrical intersysmbol interference gone • This is nice • Circuits and techniques push the envelope • ULSI gives transistors to use for I/O Optical Interconnect Workshop

  23. out; 4Gb/s 6 5 j1 j2 6 5 10b@ 400MHz j3 6 5 6 5 j10 Distribute filter DAC Clock Equalization • Pre-emphasizes signal to compensate • for attenuation • Gives flat attenuation response from 0.2 • to 2GHz • 4Gb/s over 100m Optical Interconnect Workshop W. Dally and J. Poulton

  24. Conclusions • Reviewed the SIA roadmap for I/O • I/O Impact of scaling CMOS • Circuit and system techniques • Skin effect • Equalization • CMOS circuit design, infrastructure, CAD tools, • ULSI, all favor pushing existing limits • Tends to delay optical entry at the lowest level Optical Interconnect Workshop

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