COMP541 Datapath & Single-Cycle MIPS

1. COMP541Datapath &Single-Cycle MIPS Montek Singh Oct 27, 2014

2. Topics • Complete the datapath • Add control to it • Create a full single-cycle MIPS! • Reading • Chapter 7 • Review MIPS assembly language • Chapter 6 of course textbook • Or, Patterson Hennessy (inside front flap)

3. A MIPS CPU reset clk clk memwrite dataadr readdata writedata pc Instr Memory MIPS CPU Data Memory instr

4. Top-Level: MIPS CPU + memories reset clk Top-level module reset clk clk readdata writedata dataadr memwrite pc Instr Memory MIPS CPU Data Memory instr We will add I/O devices (display, keyboard, etc.) later

5. Top-Level MIPS: Verilog module top(input clk, reset, output … ); // add signals here for debugging // we will add I/O later wire [31:0] pc, instr, readdata, writedata, dataadr; wire memwrite; mipsmips(clk, reset, pc, instr, memwrite, dataadr, writedata, readdata); // processor imemimem(pc[31:0], instr); // instr memory // send full PC to imem dmemdmem(clk, memwrite, dataadr, writedata, readdata); // data memory endmodule

6. One level down: Inside MIPS • Datapath: components that store or process data • registers, ALU, multiplexors, sign-extension, etc. • we will regard memories as outside the CPU, so not part of the core datapath • Control: components that tell datapath what to do and when • control logic (FSMs or combinational look-up tables) Control opcode, func, flagZ… ALUFN,regwrite, regdst… writedata readdata dataadr memwrite clk pc Instr Memory MIPS Datapath Data Memory MIPS CPU reset instr clk

7. One level down: Inside MIPS module mips(input clk, reset, output [31:0] pc, input [31:0] instr, output memwrite, output [31:0] dataaddr, writedata, input [31:0] readdata); wire memtoreg, branch, pcsrc, alusrc, regdst, regwrite, jump; wire [4:0] ALUFN; wire flagZ; controller c(instr[31:26], instr[5:0], flagZ, memtoreg, memwrite, pcsrc, alusrc, regdst, regwrite, jump, ALUFN); datapathdp(clk, reset, memtoreg, pcsrc, alusrc, regdst, regwrite, jump, ALUFN, flagZ, pc, instr, dataddr, writedata, readdata); endmodule NOTE: This is may need changes before you use it for your lab assignment

8. Review: MIPS instruction types Three instruction formats: R-Type: register operands I-Type: immediate operand J-Type: for jumps

9. R-Type instructions • Register-type • 3 register operands: • rs, rt: source registers • rd: destination register • Other fields: • op: the operation code or opcode (0 for R-type instructions) • funct: the function • together, op and funct tell the computer which operation to perform • shamt: the shift amount for shift instructions, otherwise itis 0

10. R-Type Examples Note the order of registers in the assembly code: add rd, rs, rt

11. I-Type instructions • Immediate-type • 3 operands: • op: the opcode • rs, rt: register operands • imm: 16-bit two’s complement immediate

12. I-Type Examples Note the differing order of registers in the assembly and machine codes: addi rt, rs, imm lw rt, imm(rs) sw rt, imm(rs)

13. J-Type instructions • Jump-type • 26-bit address operand (addr) • Used for jump instructions (j)

14. Review: Instruction Formats

15. MIPS State Elements • We will fill out the datapath and control logic for basic single cycle MIPS • first the datapath • then the control logic

16. Single-Cycle Datapath: lw • Let’s start by implementing lw instruction • How does lwwork? • STEP 1: Fetch instruction

17. Single-Cycle Datapath: lw • STEP 2: Read source operands from register file

18. Single-Cycle Datapath: lw • STEP 3: Sign-extend the immediate • NOTE: Sign Extension is done conditionally in our MIPS • there are signed and unsigned instructions (e.g., ADD vs. XOR)

19. Single-Cycle Datapath: lw • STEP 4: Compute the memory address Note ALUControl: ours will be different

20. Single-Cycle Datapath: lw • STEP 5: Read data from memory and write it back to register file

21. Single-Cycle Datapath: lw • STEP 6: Determine the address of the next instruction

22. Let’s be Clear: CPU is Single-Cycle! • Although the slides said “STEP” … • … all those operations are performed in one cycle!!! • Let’s look at sw next … • … and then R-type instructions

23. Single-Cycle Datapath: sw • Write data in rt to memory • nothing is written back into the register file

24. Single-Cycle Datapath: R-type instr • R-Type instructions: • Read from rs and rt • Write ALUResult to register file • Write to rd (instead of rt)

25. Single-Cycle Datapath: beq • Determine whether values in rs and rt are equal • Calculate branch target address: BTA = (sign-extended immediate << 2) + (PC+4)

26. Complete Single-Cycle Processor (w/control)

27. Control Unit • Generally as shown below • but some differences because our ALU is more sophisticated Note: Zero flag is input to control, and PCSrc is generated here! flagZ Note: This will be different for our full-feature ALU! PCSrc Note: This will be 5 bits for our full-feature ALU!

28. Review: Lightweight ALU from book

29. Review: Lightweight ALU from book

30. Review: Our “full feature” ALU A B Sub Boolean Bidirectional Shifter Add/Sub Bool 1 0 Shft Math 1 0 Result • Our ALU from Lab 3 (with support for comparisons) 5-bit ALUFN Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B 1 X0 1 1 A LT B 1 X1 1 1 A LTU B X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B <? 0 1 FlagsN,V,C Bool0 Z Flag

31. Review: R-Type instructions • Register-type • 3 register operands: • rs, rt: source registers • rd: destination register • Other fields: • op: the operation code or opcode (0 for R-type instructions) • funct: the function • together, op and funct tell the computer which operation to perform • shamt: the shift amount for shift instructions, otherwise itis 0

32. Controller (2 modules) module controller(input [5:0] op, funct, input flagZ, output memtoreg, memwrite, output pcsrc, alusrc, output regdst, regwrite, output jump, output [2:0] alucontrol); // 5 bit ALUFN for our ALU!! wire [1:0] aluop; // This will be different for our ALU wire branch; // See NOTE on next slide maindecmd(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop); aludec ad(funct, aluop, alucontrol); assign pcsrc = branch & (op == beq ? flagZ : ~flagZ); // handle both beq and bne endmodule flagsZ PCSrc

33. Note on Controller Implementation • For Lab: we will merge the functionality of the main decoder and ALU decoder into one • so, okay not to partition into two submodules

34. Main Decoder module maindec(input [5:0] op, output memtoreg, memwrite, branch, alusrc, output regdst, regwrite, jump, output [1:0] aluop); // different for our ALU reg [8:0] controls; assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, jump, aluop} = controls; always @(*) case(op) 6'b000000: controls <= 9'b110000010; //Rtype 6'b100011: controls <= 9'b101001000; //LW 6'b101011: controls <= 9'b001010000; //SW 6'b000100: controls <= 9'b000100001; //BEQ 6'b001000: controls <= 9'b101000000; //ADDI 6'b000010: controls <= 9'b000000100; //J default: controls <= 9'bxxxxxxxxx; //TIP: put controls for NOP here! endcase endmodule Why do this? This entire coding may be different in our design

35. ALU Decoder module aludec(input [5:0] funct, input [1:0] aluop, output reg [2:0] alucontrol); // 5 bits for our ALU!! always @(*) case(aluop) 2'b00: alucontrol <= 3'b010; // add 2'b01: alucontrol <= 3'b110; // sub default: case(funct) // RTYPE 6'b100000: alucontrol <= 3'b010; // ADD 6'b100010: alucontrol <= 3'b110; // SUB 6'b100100: alucontrol <= 3'b000; // AND 6'b100101: alucontrol <= 3'b001; // OR 6'b101010: alucontrol <= 3'b111; // SLT default: alucontrol <= 3'bxxx; // ??? endcase endcase endmodule This entire coding will be different in our design

36. Control Unit: ALU Decoder This entire coding will be different in our design

37. Control Unit: Main Decoder

38. Note on controller • The actual number and names of control signals may be somewhat different in our/your design • compared to the one given in the book • because we are implementing more features/instructions • SO BE VERY CAREFUL WHEN YOU DESIGN YOUR CPU!

39. Single-Cycle Datapath Example: or

40. Extended Functionality: addi • No change to datapath

41. Control Unit: addi

42. Adding Jumps: j

43. Control Unit: Main Decoder

44. Summary • We learned about a complete MIPS CPU • NOTE: Many details are different… • … from what you will implement in the lab • our lab MIPS has more features • every single line of Verilog you take from these slides must be carefully vetted! • Next class: • We will look at performance of single-cycle MIPS • We will look at multi-cycle MIPS to improve performance • Next lab: • Implement single-cycle CPU!