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A Novel Random Access Scan Flip-Flop Design

A Novel Random Access Scan Flip-Flop Design. Anand S. Mudlapur Vishwani D. Agrawal (Speaker) Adit D. Singh Department of Electrical and Computer Engineering Auburn University, AL 36849, USA. Ninth VLSI Design and Test Symposium – VDAT ’05 Bangalore, 10-13, 2005.

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A Novel Random Access Scan Flip-Flop Design

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  1. A Novel Random Access Scan Flip-Flop Design Anand S. Mudlapur Vishwani D. Agrawal (Speaker) Adit D. Singh Department of Electrical and Computer Engineering Auburn University, AL 36849, USA Ninth VLSI Design and Test Symposium – VDAT ’05 Bangalore, 10-13, 2005 Mudlapur et al.: VDAT'05

  2. Motivation for This Work • Conventional serial scan (SS) test sequences are increasing rapidly to an unimaginable quantity leading to long test time. • Scan-in and scan-out result in high switching activity during test. • Reduction of power and test time are complimentary objectives in serial scan. Mudlapur et al.: VDAT'05

  3. Outline • Introduction • The RAS solution and a unique “toggle” Flip-Flop design • Advantage of our design in eliminating two global signals • Results on ISCAS Benchmark Circuits • Conclusion Mudlapur et al.: VDAT'05

  4. Introduction • Random Access Scan (RAS) offers a single solution to the problems faced by serial scan (SS): • Each RAS cell is uniquely addressable for read or write. • RAS reduces test application time and test power which are otherwise complimentary objectives. • Publications on RAS: • Ando, COMPCON-80 • Wagner, COMPCON-83 • Baik et al., VLSI Design-04 • Mudlapur et al., ITC-05 • Disadvantage: High routing overhead – test control, address and scan-in signals must be routed to all flip-flops. Mudlapur et al.: VDAT'05

  5. Serial Scan (SS) Combinational Circuit PI PO Scan-in Scan-out FF FF FF Test control (TC) Example: Consider a circuit with 5,000 FFs and 10,000 combinational test vectors Total test cycles = 5,000 x 10,000 + 10,000 + 5,000 =50,015,000 Mudlapur et al.: VDAT'05

  6. Random Access Scan (RAS) Combinational Circuit PI PO Address Inputs FF FF FF Scan-out bus Decoder Scan-in These signals are eliminated in our design TC During every test, only a subset of all Flip-flops needs to be set and observed for targeted faults Mudlapur et al.: VDAT'05

  7. The “Toggle” RAS Flip-Flop To Combinational Logic M S M U X Combinational Logic Data To Scan-out Bus Clock x y RAS-FF √nff Lines √nff Lines Decoded address lines Row Decoder Column Decoder Address (log2nff) Mudlapur et al.: VDAT'05

  8. Toggle Flip-Flop Operation Mudlapur et al.: VDAT'05

  9. Toggle Flip-Flop Operation (contd.) Unaddressed FFs Addressed FF RAS FF 0 RAS FF 1 RAS FF 1 RAS FF 0 Decoded address lines Mudlapur et al.: VDAT'05

  10. Macro Level Idea of Signals to RAS-FF RAS FF11 RAS FF12 RAS FF13 RAS FF14 D-FF x1 D-FF RAS FF21 RAS FF22 RAS FF23 RAS FF24 D-FF x2 D-FF To Next Level RAS FF31 RAS FF32 RAS FF33 RAS FF34 D-FF x3 D-FF RAS FF41 RAS FF42 RAS FF43 RAS FF44 D-FF x4 D-FF y1 y2 y3 y4 Mudlapur et al.: VDAT'05

  11. Gate Area Overhead Gate area overhead of Serial Scan = Gate area overhead of Random Access Scan = nff – Number of Flip-Flops ng – Number of Gates Mudlapur et al.: VDAT'05

  12. Gate Area Overhead (Example) A circuit with 5,120 gates and 512 FFs Gate overhead of serial scan = 20 % Gate overhead of RAS = 30.2 % A circuit with 20,480 gates and 512 FFs Gate overhead of serial scan = 8 % Gate overhead of RAS = 12 % Mudlapur et al.: VDAT'05

  13. Overhead in terms of Transistors Gate area overhead of Serial Scan = Gate area overhead of Random Access Scan = Synthesis performed on SUN ULTRA 5 Machine RAS has 16 transistors more than SS Flip-Flop Mudlapur et al.: VDAT'05

  14. Results Mudlapur et al.: VDAT'05

  15. Results (Contd.) Mudlapur et al.: VDAT'05

  16. Conclusion • New design of a “Toggle” Flip-Flop reduces the RAS routing overhead. • A proposed RAS architecture with new FF has several other advantages: • Algorithmic minimization reduces test cycles by 60%. • Power dissipation during test is reduced by 99%. • For details, see Mudlapur et al., ITC-05. Mudlapur et al.: VDAT'05

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