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Iris Simulator Overview

Iris Simulator Overview. Mitchelle Rasquinha CASL, School of ECE Georgia Institute of Technology. ece8813a 7 th Sept 2010. Simulator Basics. Network Simulator Router Micro-architecture design. Network topology design. Discrete Event Simulator (DES)

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Iris Simulator Overview

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  1. Iris Simulator Overview MitchelleRasquinha CASL, School of ECE Georgia Institute of Technology ece8813a 7th Sept 2010

  2. Simulator Basics • Network Simulator • Router Micro-architecture design. • Network topology design. • Discrete Event Simulator (DES) • Will highlight specific kernel api’s that need to be used. • Component Library • Interfaces for models such as a buffer, arbiter, crossbar etc are defined. ( Make sure to inherit from these base classes when you add new models.) • As part of the assignment you will need to add a new router model to the component library. Georgia Institute of Technology

  3. Simulator Setup • Has been used on Red hat and Ubuntu distributions of linux • Cppprogramming language; Compiles with gcc 4.3 and above. • Help at http://wiki.github.com/iris-casl/manifold/ • Doxygen documentation: http://iris-casl.github.com/ • Compilation • Download the source from the downloads section (ece8813a_hw1.tgz) • Untar the source • Compile the source • Example run: • How to add new files: Add them to the Makefile.am and use automake or use the auto_gen.sh script. Detailed instructions on the build tools/environment can be found on the wiki page at http://wiki.github.com/iris-casl/manifold/ Georgia Institute of Technology

  4. Terminology Components • Terminals, Interfaces, Routers T Router T I Int Topology: Routers connected to each other via links. Pseudo-Components T I • Router • Buffers • RC Unit • Arbiters • Crossbar • Interface • Buffers • Arbiters • Terminal • Packet Generators • Another Simulator! Georgia Institute of Technology

  5. Code Structure • Traces if you are using the trace packet generator for a terminal node. • Config: Simulator knobs. • Refruns: some sample runs and reference outputs. • Frontend: Instantiation of simulator objects and topology creation. • Util: variables for the simulator knobs • data_types: Packet Formats • components: Component Library Models • Routers, Arbiters, Buffers etc. • Interfaces has the base classes for a generic model. • The actual models are in impl Georgia Institute of Technology

  6. Simulation Methodology Terminal nodes and time stepped components schedule an event for time = 1. read_config() create_components() connect_components() loop <all_components>{component_ptr->setup();} Simulator::StopAt(max_sim_time); Simulator::Run(); loop <all_components> {component_ptr->print_stats(); } delete components(); exit(0); • DES: advance simulation by generating future events Simulator::Schedule( Simulator::Now()+1, <func_callback> ,<obj_ptr>, <args_for_func>); Generic Form of schedule used in Iris Simulator::Schedule( Simulator::Now()+1, NetworkComponent::process_event,<obj_ptr>, IrisEvent*); time =cycle1 time =cycle2 time =cycle3 main() Kernel process event queue. Kernel processes all events for time=t and then ticks to time=t+1. Order of events at time ‘t’ is dependent on how they were scheduled. Georgia Institute of Technology

  7. Eg: GenericRouterBase Simulator call back function pseudo components event_handlers Georgia Institute of Technology

  8. Example Router Model swa,vca decoder[p0] in_buffer[p0] input_buffer_state[p0][vc0] xbar downstream_credits Georgia Institute of Technology

  9. Eg: GenericRouterBaseEvents Incoming interface to the router. Pseudo components have useful functions such as in_buffer[3]->change_push_channel(2); in_buffer[3].push(flit_ptr); Pipe stages in backward order Georgia Institute of Technology

  10. Conclusion • To get started • “GenericRouterBase” add VCT. • “GenericTracePktGen” modify traffic pattern. • Config increase no of vcs and add additional counters. • Existing code has flit level flow control and pkt level flow control. • downstream_credits in router class [ flit level ] • ready_signal in interface class [ pkt level ] • Some debugging hooks already exist • detect_deadlock(); • Break if a flit was sent out and the credit dint comeback for >1000 cycles. • Use the google group for questions • ece8813a-fall2010 • tar is in the downloads section of the group. • Warning: Get started early! Georgia Institute of Technology

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